VHDL初心者のためのコンポーネント活用法10選

-- コンポーネントの定義
COMPONENT comp_name
PORT(
    input : IN bit_vector;
    output : OUT bit_vector
);
END COMPONENT;

ENTITY main IS
PORT(
    main_input : IN bit_vector(7 DOWNTO 0);
    main_output : OUT bit_vector(7 DOWNTO 0)
);
END ENTITY main;

ARCHITECTURE behavior OF main IS
    -- comp_nameのコンポーネントを使用
    SIGNAL temp : bit_vector(7 DOWNTO 0);

    BEGIN
    comp_instance : comp_name
    PORT MAP(
        input => main_input,
        output => temp
    );

    main_output <= temp;
END ARCHITECTURE behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity MultiComponent is
end MultiComponent;

architecture Behavior of MultiComponent is
    signal inter_signal1 : std_logic;
    signal inter_signal2 : std_logic;

    -- コンポーネントの宣言
    component Comp1
    port (
        input1 : in std_logic;
        output1 : out std_logic
    );
    end component;

    component Comp2
    port (
        input2 : in std_logic;
        output2 : out std_logic
    );
    end component;

begin
    -- コンポーネントのインスタンス化
    comp1_instance : Comp1
    port map(
        input1 => inter_signal1,
        output1 => inter_signal2
    );

    comp2_instance : Comp2
    port map(
        input2 => inter_signal2,
        output2 => inter_signal1
    );

end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mainEntity is
    Port ( input_signal  : in  STD_LOGIC;
           output_signal : out STD_LOGIC);
end mainEntity;

architecture Behavioral of mainEntity is

    component SampleComponent
        Port ( comp_input  : in  STD_LOGIC;
               comp_output : out STD_LOGIC);
    end component;

begin

    myComponent : SampleComponent
        port map (
            comp_input  => input_signal,
            comp_output => output_signal
        );

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mainEntity is
    Port ( input_signal1 : in  STD_LOGIC;
           input_signal2 : in  STD_LOGIC;
           output_signal : out STD_LOGIC);
end mainEntity;

architecture Behavioral of mainEntity is

    component AdvancedComponent
        Port ( adv_input1  : in  STD_LOGIC;
               adv_input2  : in  STD_LOGIC;
               adv_output  : out STD_LOGIC);
    end component;

begin

    myAdvancedComp : AdvancedComponent
        port map (
            adv_input1  => input_signal1,
            adv_input2  => input_signal2,
            adv_output  => output_signal
        );

end Behavioral;

entity adder is
    generic ( BIT_WIDTH : integer := 8 );
    port ( A, B : in  std_logic_vector(BIT_WIDTH-1 downto 0);
           SUM : out std_logic_vector(BIT_WIDTH-1 downto 0) );
end entity adder;

architecture behavior of adder is
begin
    -- 加算処理の記述
    SUM <= A + B;
end architecture behavior;

component adder
    generic ( BIT_WIDTH : integer := 16 );
    port ( A, B : in  std_logic_vector(BIT_WIDTH-1 downto 0);
           SUM : out std_logic_vector(BIT_WIDTH-1 downto 0) );
end component;

-- 状態機械を持つコンポーネントの定義
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity StateMachine is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           input_signal : in STD_LOGIC;
           output_signal : out STD_LOGIC);
end StateMachine;

architecture Behavior of StateMachine is
    -- 状態の定義
    type State_Type is (STATE1, STATE2);
    signal current_state, next_state : State_Type;

begin
    process(clk, rst)
    begin
        if rst = '1' then
            current_state <= STATE1;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process(current_state, input_signal)
    begin
        case current_state is
            when STATE1 =>
                output_signal <= '0';
                if input_signal = '1' then
                    next_state <= STATE2;
                else
                    next_state <= STATE1;
                end if;
            when STATE2 =>
                output_signal <= '1';
                if input_signal = '0' then
                    next_state <= STATE1;
                else
                    next_state <= STATE2;
                end if;
        end case;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity StateMachine_tb is
end StateMachine_tb;

architecture sim of StateMachine_tb is
    signal clk, rst, input_signal, output_signal : STD_LOGIC;
    component StateMachine
        Port ( clk : in STD_LOGIC;
               rst : in STD_LOGIC;
               input_signal : in STD_LOGIC;
               output_signal : out STD_LOGIC);
    end component;
begin
    UUT: StateMachine port map (clk, rst, input_signal, output_signal);

    process
    begin
        clk <= '0', '1' after 10 ns;
        wait for 20 ns;
    end process;

    process
    begin
        rst <= '1';
        wait for 30 ns;
        rst <= '0';
        wait for 50 ns;
        rst <= '1';
        wait;
    end process;

    process
    begin
        wait for 40 ns;
        input_signal <= not input_signal;
        wait for 20 ns;
        input_signal <= not input_signal;
        wait for 20 ns;
        input_signal <= not input_signal;
        wait;
    end process;
end sim;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity ArithmeticComponent is
    Port ( A : in STD_LOGIC_VECTOR(7 downto 0);
           B : in STD_LOGIC_VECTOR(7 downto 0);
           Sum : out STD_LOGIC_VECTOR(7 downto 0));
end ArithmeticComponent;

architecture Behavior of ArithmeticComponent is
begin
    process(A, B)
    begin
        Sum <= A + B;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock_divider is
    Port ( clk_in : in STD_LOGIC;  -- 入力クロック
           clk_out : out STD_LOGIC;  -- 出力クロック
           reset : in STD_LOGIC);  -- リセット信号
end clock_divider;

architecture Behavioral of clock_divider is
    signal count : integer range 0 to 4 := 0;  -- カウンタ
begin
    process(clk_in, reset)
    begin
        if reset = '1' then  -- リセット時
            clk_out <= '0';
            count <= 0;
        elsif rising_edge(clk_in) then  -- クロックの立ち上がりエッジで
            if count = 4 then  -- カウンタが4になったら
                clk_out <= not clk_out;  -- クロック出力をトグル
                count <= 0;
            else
                count <= count + 1;
            end if;
        end if;
    end process;
end Behavioral;

-- 外部からの分周比選択信号を追加
Port ( div_ratio : in integer range 1 to 10;
      ...
);

...

if count = div_ratio then  -- カウンタがdiv_ratioになったら
    clk_out <= not clk_out;
    count <= 0;
else
    count <= count + 1;
end if;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MemoryMapping is
    Port ( addr : in std_logic_vector(3 downto 0);
           wr   : in std_logic;
           data_in  : in std_logic_vector(7 downto 0);
           data_out : out std_logic_vector(7 downto 0));
end MemoryMapping;

architecture Behavioral of MemoryMapping is
    signal memory : std_logic_vector(7 downto 0) := (others => '0');

begin
    process(addr, wr, data_in)
    begin
        -- メモリアドレスに応じて読み書きを行います
        if wr = '1' then
            memory := data_in;
        else
            data_out <= memory;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0));
end counter;

architecture Behavioral of counter is
    signal cnt: STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    process(clk, reset)
    begin
        -- リセット処理
        if reset = '1' then
            cnt <= "0000";
        -- クロック立ち上がり時のカウントアップ処理
        elsif rising_edge(clk) then
            cnt <= cnt + 1;
        end if;
    end process;
    count <= cnt;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity counter_tb is
end counter_tb;

architecture sim of counter_tb is
    signal clk: STD_LOGIC := '0';
    signal reset: STD_LOGIC := '0';
    signal count: STD_LOGIC_VECTOR(3 downto 0);
    component counter
        Port ( clk : in STD_LOGIC;
               reset : in STD_LOGIC;
               count : out STD_LOGIC_VECTOR(3 downto 0));
    end component;
begin
    UUT: counter port map(clk, reset, count);
    clk_proc: process
    begin
        wait for 10 ns;
        clk <= not clk;
    end process;
    reset_proc: process
    begin
        reset <= '1';
        wait for 20 ns;
        reset <= '0';
        wait;
    end process;
end sim;

-- コンポーネント宣言
component my_component is
    port (
        A : in std_logic;
        B : in std_logic;
        C : out std_logic
    );
end component;

-- コンポーネントのインスタンス化
U1: my_component port map (
    A => signal_A,
    B => signal_B
);

generic (
    WIDTH : integer := 8
);
port (
    A : in std_logic_vector(WIDTH-1 downto 0);
    B : in std_logic_vector(WIDTH-1 downto -1); -- ここが誤り
    C : out std_logic_vector(WIDTH-1 downto 0)
);

generic (
    WIDTH : integer := 16
);
port (
    A : in std_logic_vector(WIDTH-1 downto 0);
    B : out std_logic_vector(WIDTH-1 downto 0)
);

-- 中略

U1: my_component generic map (WIDTH => 32) port map (
    A => signal_A,
    B => signal_B
);