VHDLでマスターするサブモジュールの10の使い方

ENTITY and_gate IS
    PORT(A, B : IN BIT; Y : OUT BIT);
END ENTITY and_gate;

ARCHITECTURE behavior OF and_gate IS
BEGIN
    Y <= A AND B;
END ARCHITECTURE behavior;

ENTITY or_gate IS
    PORT(A, B : IN BIT; Y : OUT BIT);
END ENTITY or_gate;

ARCHITECTURE behavior OF or_gate IS
BEGIN
    Y <= A OR B;
END ARCHITECTURE behavior;

ENTITY clk_gen IS
    PORT(clk_in : IN BIT; clk_out : OUT BIT);
END ENTITY clk_gen;

ARCHITECTURE behavior OF clk_gen IS
BEGIN
    PROCESS(clk_in)
    BEGIN
        IF rising_edge(clk_in) THEN
            clk_out <= NOT clk_out;
        END IF;
    END PROCESS;
END ARCHITECTURE behavior;

ENTITY counter IS
    PORT(clk : IN BIT; rst : IN BIT; count : OUT BIT_VECTOR(3 DOWNTO 0));
END ENTITY counter;

ARCHITECTURE behavior OF counter IS
    SIGNAL tmp_count : BIT_VECTOR(3 DOWNTO 0) := "0000";
BEGIN
    PROCESS(clk, rst)
    BEGIN
        IF rst = '1' THEN
            tmp_count <= "0000";
        ELSIF rising_edge(clk) THEN
            IF tmp_count = "1111" THEN
                tmp_count <= "0000";
            ELSE
                tmp_count <= tmp_count + 1;
            END IF;
        END IF;
    END PROCESS;
    count <= tmp_count;
END ARCHITECTURE behavior;

ENTITY fifo IS
    PORT(data_in : IN BIT_VECTOR(3 DOWNTO 0);
         write_enable, read_enable : IN BIT;
         data_out : OUT BIT_VECTOR(3 DOWNTO 0));
END ENTITY fifo;

ARCHITECTURE behavior OF fifo IS
    TYPE fifo_array IS ARRAY(0 TO 3) OF BIT_VECTOR(3 DOWNTO 0);
    SIGNAL buffer : fifo_array := (others => "0000");
    SIGNAL write_ptr, read_ptr : INTEGER := 0;
BEGIN
    PROCESS(write_enable, read_enable)
    BEGIN
        IF write_enable = '1' THEN
            buffer(write_ptr) <= data_in;
            IF write_ptr < 3 THEN
                write_ptr <= write_ptr + 1;
            ELSE
                write_ptr <= 0;
            END IF;
        END IF;

        IF read_enable = '1' THEN
            data_out <= buffer(read_ptr);
            IF read_ptr < 3 THEN
                read_ptr <= read_ptr + 1;
            ELSE
                read_ptr <= 0;
            END IF;
        END IF;
    END PROCESS;
END ARCHITECTURE behavior;

ENTITY state_machine IS
    PORT(clk, start : IN BIT; state_out : OUT INTEGER);
END ENTITY state_machine;

ARCHITECTURE behavior OF state_machine IS
    TYPE states IS (state1, state2, state3);
    SIGNAL current_state, next_state : states := state1;
BEGIN
    PROCESS(clk)
    BEGIN
        IF rising_edge(clk) THEN
            current_state <= next_state;
        END IF;
    END PROCESS;

    PROCESS(current_state, start)
    BEGIN
        CASE current_state IS
            WHEN state1 =>
                IF start = '1' THEN
                    next_state <= state2;
                ELSE
                    next_state <= state1;
                END IF;
            WHEN state2 =>
                next_state <= state3;
            WHEN state3 =>
                next_state <= state1;
        END CASE;
    END PROCESS;

    PROCESS(current_state)
    BEGIN
        CASE current_state IS
            WHEN state1 =>
                state_out <= 1;
            WHEN state2 =>
                state_out <= 2;
            WHEN state3 =>
                state_out <= 3;
        END CASE;
    END PROCESS;
END ARCHITECTURE behavior;

ENTITY adder IS
    PORT(A, B : IN BIT_VECTOR(3 DOWNTO 0); SUM : OUT BIT_VECTOR(3 DOWNTO 0));
END ENTITY adder;

ARCHITECTURE behavior OF adder IS
BEGIN
    SUM <= A + B;
END ARCHITECTURE behavior;

ENTITY subtractor IS
    PORT(A, B : IN BIT_VECTOR(3 DOWNTO 0); DIFF : OUT BIT_VECTOR(3 DOWNTO 0));
END ENTITY subtractor;

ARCHITECTURE behavior OF subtractor IS
BEGIN
    DIFF <= A - B;
END ARCHITECTURE behavior;

ENTITY multiplier IS
    PORT(A, B : IN BIT_VECTOR(1 DOWNTO 0); PROD : OUT BIT_VECTOR(3 DOWNTO 0));
END ENTITY multiplier;

ARCHITECTURE behavior OF multiplier IS
BEGIN
    PROD <= A * B;
END ARCHITECTURE behavior;

ENTITY divider IS
    PORT(A : IN BIT_VECTOR(3 DOWNTO 0); B : IN BIT_VECTOR(1 DOWNTO 0);
          QUOTIENT : OUT BIT_VECTOR(1 DOWNTO 0); REMAINDER : OUT BIT_VECTOR(1 DOWNTO 0));
END ENTITY divider;

ARCHITECTURE behavior OF divider IS
BEGIN
    QUOTIENT <= A / B;
    REMAINDER <= A MOD B;
END ARCHITECTURE behavior;