VHDL初期値完全マスター！7つのサンプルコードで理解

type vector_array is array (0 to 3) of std_logic_vector(7 downto 0);
signal example_array : vector_array := (others => "00000000");

entity example_circuit is
port (
    rst : in std_logic;
    clk : in std_logic;
    out_signal : out std_logic
);
end entity example_circuit;

architecture behavior of example_circuit is
signal internal_signal : std_logic := '0';
begin
    process(clk, rst)
    begin
        if rst = '1' then
            internal_signal <= '0';
        elsif rising_edge(clk) then
            internal_signal <= not internal_signal;
        end if;
    end process;

    out_signal <= internal_signal;
end architecture behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Adder is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0) := "00000000";  --初期値を0として設定
           B : in  STD_LOGIC_VECTOR(7 downto 0) := "00000000";  --初期値を0として設定
           SUM : out  STD_LOGIC_VECTOR(7 downto 0));
end Adder;

architecture Behavioral of Adder is
begin
    SUM <= A + B;  -- AとBの加算結果をSUMに代入
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ConditionCheck is
    Port ( X : in  STD_LOGIC_VECTOR(7 downto 0) := "00000101";  --初期値を5として設定
           Y : out STD_LOGIC);
end ConditionCheck;

architecture Behavioral of ConditionCheck is
begin
process(X)
    begin
        if X = "00000101" then  -- Xが5の場合
            Y <= '1';  -- Yを1に設定
        else
            Y <= '0';  -- それ以外の場合はYを0に設定
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity loop_example is
Port ( clk : in STD_LOGIC;
       data_out : out STD_LOGIC_VECTOR(9 downto 0));
end loop_example;

architecture Behavioral of loop_example is
signal data : STD_LOGIC_VECTOR(9 downto 0) := (others => '0');
begin
process(clk)
begin
  if rising_edge(clk) then
    for i in 0 to 9 loop
      -- ここでは、iの値に基づいて、初期値を設定しています。
      data(i) <= conv_std_logic_vector(i, 10);
    end loop;
  end if;
end process;

data_out <= data;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiple_initial_values is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           output_A : out STD_LOGIC;
           output_B : out STD_LOGIC);
end multiple_initial_values;

architecture Behavioral of multiple_initial_values is
    signal signal_A : STD_LOGIC := '0';  -- 初期値として'0'を設定
    signal signal_B : STD_LOGIC := '1';  -- 初期値として'1'を設定
begin
    process(clk, rst)
    begin
        if rst = '1' then
            signal_A <= '0';
            signal_B <= '1';
        elsif rising_edge(clk) then
            signal_A <= not signal_A;
            signal_B <= not signal_B;
        end if;
    end process;

    output_A <= signal_A;
    output_B <= signal_B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample is
end sample;

architecture Behavioral of sample is
    signal test_signal : std_logic_vector(7 downto 0) := 255; -- ここでエラー
begin
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample is
end sample;

architecture Behavioral of sample is
    signal test_signal : std_logic_vector(2 downto 0) := "1001"; -- ここでエラー
begin
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample is
end sample;

architecture Behavioral of sample is
    signal test_signal : std_logic_vector(0 to 7) := "11001010"; 
begin
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample_entity is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_out : out STD_LOGIC_VECTOR(7 downto 0) );
end sample_entity;

architecture Behavioral of sample_entity is
    signal data : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- ここで初期値を設定
begin
    process(clk, rst)
    begin
        if rst = '1' then
            data <= "00000000"; -- リセット時の値
        elsif rising_edge(clk) then
            data <= data + 1;
        end if;
    end process;

    data_out <= data;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample_entity2 is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_out1 : out STD_LOGIC_VECTOR(7 downto 0);
           data_out2 : out STD_LOGIC_VECTOR(7 downto 0) );
end sample_entity2;

architecture Behavioral of sample_entity2 is
    signal data1 : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- 初期値を設定
    signal data2 : STD_LOGIC_VECTOR(7 downto 0) := "11111111"; -- 別の初期値を設定
begin
    process(clk, rst)
    begin
        if rst = '1' then
            data1 <= "00000000"; -- リセット時の値
            data2 <= "11111111"; -- リセット時の値
        elsif rising_edge(clk) then
            data1 <= data1 + 1;
            data2 <= data2 - 1;
        end if;
    end process;

    data_out1 <= data1;
    data_out2 <= data2;

end Behavioral;