VHDLにおけるAND演算子の使い方と活用14選

signal A, B, C : std_logic_vector(3 downto 0);
-- 中略
C <= A and B;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity AND_Gate is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Y : out STD_LOGIC);
end AND_Gate;

architecture Behavioral of AND_Gate is
begin
    Y <= A and B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Bit_AND is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           Y : out STD_LOGIC_VECTOR(7 downto 0));
end Bit_AND;

architecture Behavioral of Bit_AND is
begin
    Y <= A and B;
end Behavioral;

A = "10101010"
B = "11001100"

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Priority_Example is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Y : out STD_LOGIC);
end Priority_Example;

architecture Behavioral of Priority_Example is
begin
    -- 優先順位を考慮した式
    Y <= (A and B) or (C and D);

    -- 以下の式は上記と同じ結果になります
    -- Y <= A and B or C and D;

    -- しかし、明示的に括弧を使用することで可読性が向上します
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Signal_AND is
    Port ( A : in  STD_LOGIC_VECTOR(3 downto 0);
           B : in  STD_LOGIC_VECTOR(3 downto 0);
           Y : out STD_LOGIC_VECTOR(3 downto 0));
end Signal_AND;

architecture Behavioral of Signal_AND is
    signal temp : STD_LOGIC_VECTOR(3 downto 0);
begin
    temp <= A and B;
    Y <= temp;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Process_AND is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           Y : out STD_LOGIC);
end Process_AND;

architecture Behavioral of Process_AND is
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            Y <= A and B;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Shift_AND is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           Y : out STD_LOGIC_VECTOR(7 downto 0));
end Shift_AND;

architecture Behavioral of Shift_AND is
begin
    Y <= (A(6 downto 0) & '0') and B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Multiple_of_Eight is
    Port ( num : in  STD_LOGIC_VECTOR(3 downto 0);
           is_multiple : out STD_LOGIC);
end Multiple_of_Eight;

architecture Behavioral of Multiple_of_Eight is
begin
    is_multiple <= not(num(0) or num(1) or num(2));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Pattern_Detector is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           input : in  STD_LOGIC;
           detected : out STD_LOGIC);
end Pattern_Detector;

architecture Behavioral of Pattern_Detector is
    type state_type is (S0, S1, S2, S3);
    signal current_state, next_state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= S0;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process(current_state, input)
    begin
        next_state <= current_state;
        detected <= '0';

        case current_state is
            when S0 =>
                if input = '1' then
                    next_state <= S1;
                end if;
            when S1 =>
                if input = '0' then
                    next_state <= S2;
                end if;
            when S2 =>
                if input = '1' then
                    next_state <= S3;
                else
                    next_state <= S0;
                end if;
            when S3 =>
                if input = '1' then
                    detected <= '1';
                end if;
                next_state <= S0;
        end case;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Complex_Condition is
    Port ( num : in  STD_LOGIC_VECTOR(7 downto 0);
           result : out STD_LOGIC);
end Complex_Condition;

architecture Behavioral of Complex_Condition is
    signal is_even : STD_LOGIC;
    signal is_in_range : STD_LOGIC;
begin
    -- 偶数判定
    is_even <= not num(0);

    -- 範囲判定 (50 <= num < 100)
    is_in_range <= '1' when (num >= 50 and num < 100) else '0';

    -- 最終結果
    result <= is_even and is_in_range;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Simple_Encryption is
    Port ( data : in  STD_LOGIC_VECTOR(7 downto 0);
           key : in  STD_LOGIC_VECTOR(7 downto 0);
           mask : in  STD_LOGIC_VECTOR(7 downto 0);
           encrypted_data : out STD_LOGIC_VECTOR(7 downto 0));
end Simple_Encryption;

architecture Behavioral of Simple_Encryption is
    signal xored_data : STD_LOGIC_VECTOR(7 downto 0);
begin
    -- XOR暗号化
    xored_data <= data xor key;

    -- AND演算子を使ったマスキング
    encrypted_data <= xored_data and mask;
end Behavioral;

entity Syntax_Error is
    Port ( A : in  STD_LOGIC
           B : in  STD_LOGIC;
           Y : out STD_LOGIC);
end Syntax_Error

architecture Behavioral of Syntax_Error is
begin
    Y <= A and B
end Behavioral;

entity Syntax_Error is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Y : out STD_LOGIC);
end Syntax_Error;

architecture Behavioral of Syntax_Error is
begin
    Y <= A and B;
end Behavioral;

entity Logic_Error is
    Port ( A : in  STD_LOGIC_VECTOR(3 downto 0);
           B : in  STD_LOGIC_VECTOR(3 downto 0);
           Y : out STD_LOGIC);
end Logic_Error;

architecture Behavioral of Logic_Error is
begin
    Y <= '1' when A > B else '0';
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Logic_Error is
    Port ( A : in  STD_LOGIC_VECTOR(3 downto 0);
           B : in  STD_LOGIC_VECTOR(3 downto 0);
           Y : out STD_LOGIC);
end Logic_Error;

architecture Behavioral of Logic_Error is
begin
    Y <= '1' when unsigned(A) > unsigned(B) else '0';
end Behavioral;

entity Simulation_Trouble is
    Port ( CLK : in  STD_LOGIC;
           D   : in  STD_LOGIC;
           Q   : out STD_LOGIC);
end Simulation_Trouble;

architecture Behavioral of Simulation_Trouble is
begin
    process(CLK)
    begin
        Q <= D;
    end process;
end Behavioral;

entity Simulation_Trouble is
    Port ( CLK : in  STD_LOGIC;
           D   : in  STD_LOGIC;
           Q   : out STD_LOGIC);
end Simulation_Trouble;

architecture Behavioral of Simulation_Trouble is
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            Q <= D;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Data_Selector is
    Port ( D0, D1, D2, D3 : in  STD_LOGIC;
           S0, S1 : in  STD_LOGIC;
           Y : out STD_LOGIC);
end Data_Selector;

architecture Behavioral of Data_Selector is
begin
    Y <= (D0 and (not S1) and (not S0)) or
         (D1 and (not S1) and S0) or
         (D2 and S1 and (not S0)) or
         (D3 and S1 and S0);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Parity_Generator is
    Port ( Data : in  STD_LOGIC_VECTOR(7 downto 0);
           Parity : out STD_LOGIC);
end Parity_Generator;

architecture Behavioral of Parity_Generator is
begin
    Parity <= Data(0) xor Data(1) xor Data(2) xor Data(3) xor
              Data(4) xor Data(5) xor Data(6) xor Data(7);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Error_Detector is
    Port ( Data : in  STD_LOGIC_VECTOR(7 downto 0);
           Expected : in  STD_LOGIC_VECTOR(7 downto 0);
           Error : out STD_LOGIC);
end Error_Detector;

architecture Behavioral of Error_Detector is
    signal diff : STD_LOGIC_VECTOR(7 downto 0);
begin
    diff <= Data xor Expected;
    Error <= diff(0) or diff(1) or diff(2) or diff(3) or
             diff(4) or diff(5) or diff(6) or diff(7);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Simple_Encryption is
    Port ( Data : in  STD_LOGIC_VECTOR(7 downto 0);
           Key : in  STD_LOGIC_VECTOR(7 downto 0);
           Encrypted : out STD_LOGIC_VECTOR(7 downto 0));
end Simple_Encryption;

architecture Behavioral of Simple_Encryption is
begin
    Encrypted <= (Data and Key) or (not Data and not Key);
end Behavioral;