VHDLによる8b10bエンコーダの実装方法と活用10選

-- 1. Vivadoを起動し、「Create Project」を選択
-- 2. プロジェクト名と保存場所を設定
-- 3. RTLプロジェクトを選択
-- 4. ターゲットデバイスを選択（使用するFPGAに合わせて）
-- 5. 新しいソースファイルを作成
--    File Name: encoder_8b10b
--    File Type: VHDL
-- 6. 「Finish」をクリックしてプロジェクト作成完了

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity encoder_8b10b is
    Port ( 
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        data_in : in STD_LOGIC_VECTOR (7 downto 0);
        k_in : in STD_LOGIC;
        data_out : out STD_LOGIC_VECTOR (9 downto 0)
    );
end encoder_8b10b;

architecture Behavioral of encoder_8b10b is
    -- ここに内部信号や定数を宣言
begin
    -- ここにエンコーダのロジックを記述
end Behavioral;

entity encoder_8b10b is
    Port ( 
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        data_in : in STD_LOGIC_VECTOR (7 downto 0);
        k_in : in STD_LOGIC;
        data_out : out STD_LOGIC_VECTOR (9 downto 0)
    );
end encoder_8b10b;

architecture Behavioral of encoder_8b10b is
    signal running_disparity : STD_LOGIC := '0';

    -- 5b/6b変換テーブル
    type conversion_table_5b6b is array (0 to 31) of STD_LOGIC_VECTOR(5 downto 0);
    constant table_5b6b : conversion_table_5b6b := (
        -- テーブルの内容をここに記述
    );

    -- 3b/4b変換テーブル
    type conversion_table_3b4b is array (0 to 7) of STD_LOGIC_VECTOR(3 downto 0);
    constant table_3b4b : conversion_table_3b4b := (
        -- テーブルの内容をここに記述
    );

begin
    encoding_process : process(clk, reset)
    begin
        if reset = '1' then
            data_out <= (others => '0');
            running_disparity <= '0';
        elsif rising_edge(clk) then
            -- エンコーディングロジックをここに実装
        end if;
    end process;
end Behavioral;

entity encoder_8b10b is
    Port ( 
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        data_in : in STD_LOGIC_VECTOR (7 downto 0);
        k_in : in STD_LOGIC;
        data_out : out STD_LOGIC_VECTOR (9 downto 0);
        disparity_out : out STD_LOGIC
    );
end encoder_8b10b;

architecture Behavioral of encoder_8b10b is
    type lut_5b6b is array(0 to 31) of std_logic_vector(5 downto 0);
    type lut_3b4b is array(0 to 7) of std_logic_vector(3 downto 0);

    constant lut_5b6b_pos : lut_5b6b := (
        -- 5b/6b positive disparity lookup table
    );

    constant lut_5b6b_neg : lut_5b6b := (
        -- 5b/6b negative disparity lookup table
    );

    constant lut_3b4b_pos : lut_3b4b := (
        -- 3b/4b positive disparity lookup table
    );

    constant lut_3b4b_neg : lut_3b4b := (
        -- 3b/4b negative disparity lookup table
    );

    signal running_disparity : STD_LOGIC := '0';
    signal encoded_5b6b : STD_LOGIC_VECTOR(5 downto 0);
    signal encoded_3b4b : STD_LOGIC_VECTOR(3 downto 0);

begin
    encoding_process : process(clk, reset)
    begin
        if reset = '1' then
            running_disparity <= '0';
            data_out <= (others => '0');
        elsif rising_edge(clk) then
            if running_disparity = '0' then
                encoded_5b6b <= lut_5b6b_neg(to_integer(unsigned(data_in(4 downto 0))));
                encoded_3b4b <= lut_3b4b_neg(to_integer(unsigned(data_in(7 downto 5))));
            else
                encoded_5b6b <= lut_5b6b_pos(to_integer(unsigned(data_in(4 downto 0))));
                encoded_3b4b <= lut_3b4b_pos(to_integer(unsigned(data_in(7 downto 5))));
            end if;

            data_out <= encoded_5b6b & encoded_3b4b;

            -- Update running disparity
            running_disparity <= calculate_new_disparity(encoded_5b6b, encoded_3b4b);
        end if;
    end process;
end Behavioral;

function calculate_new_disparity(
    encoded_5b6b : STD_LOGIC_VECTOR(5 downto 0);
    encoded_3b4b : STD_LOGIC_VECTOR(3 downto 0)
) return STD_LOGIC is
    variable ones_count : integer;
begin
    ones_count := 0;
    for i in encoded_5b6b'range loop
        if encoded_5b6b(i) = '1' then
            ones_count := ones_count + 1;
        end if;
    end loop;
    for i in encoded_3b4b'range loop
        if encoded_3b4b(i) = '1' then
            ones_count := ones_count + 1;
        end if;
    end loop;

    if ones_count > 5 then
        return '1';  -- Positive disparity
    elsif ones_count < 5 then
        return '0';  -- Negative disparity
    else
        return not running_disparity;  -- Flip current disparity
    end if;
end function;

entity decoder_8b10b is
    Port ( 
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        data_in : in STD_LOGIC_VECTOR (9 downto 0);
        data_out : out STD_LOGIC_VECTOR (7 downto 0);
        k_out : out STD_LOGIC;
        error : out STD_LOGIC
    );
end decoder_8b10b;

architecture Behavioral of decoder_8b10b is
    type lut_6b5b is array(0 to 63) of std_logic_vector(4 downto 0);
    type lut_4b3b is array(0 to 15) of std_logic_vector(2 downto 0);

    constant lut_6b5b_decode : lut_6b5b := (
        -- 6b/5b decoding lookup table
    );

    constant lut_4b3b_decode : lut_4b3b := (
        -- 4b/3b decoding lookup table
    );

    signal running_disparity : STD_LOGIC := '0';

begin
    decoding_process : process(clk, reset)
        variable decoded_6b5b : STD_LOGIC_VECTOR(4 downto 0);
        variable decoded_4b3b : STD_LOGIC_VECTOR(2 downto 0);
    begin
        if reset = '1' then
            data_out <= (others => '0');
            k_out <= '0';
            error <= '0';
            running_disparity <= '0';
        elsif rising_edge(clk) then
            decoded_6b5b := lut_6b5b_decode(to_integer(unsigned(data_in(9 downto 4))));
            decoded_4b3b := lut_4b3b_decode(to_integer(unsigned(data_in(3 downto 0))));

            data_out <= decoded_6b5b & decoded_4b3b;

            -- Check for special characters and update k_out
            k_out <= is_special_character(data_in);

            -- Update running disparity and check for errors
            running_disparity <= update_disparity(data_in, running_disparity);
            error <= check_for_errors(data_in, running_disparity);
        end if;
    end process;
end Behavioral;

function check_for_errors(
    data_in : STD_LOGIC_VECTOR(9 downto 0);
    current_disparity : STD_LOGIC
) return STD_LOGIC is
    variable error : STD_LOGIC := '0';
    variable ones_count : integer := 0;
begin
    -- Count number of ones
    for i in data_in'range loop
        if data_in(i) = '1' then
            ones_count := ones_count + 1;
        end if;
    end loop;

    -- Check for invalid code words
    if ones_count = 0 or ones_count = 10 then
        error := '1';
    end if;

    -- Check for disparity errors
    if (current_disparity = '0' and ones_count > 6) or
       (current_disparity = '1' and ones_count < 4) then
        error := '1';
    end if;

    return error;
end function;

type decoder_state is (IDLE, DECODING, ERROR_HANDLING);
signal current_state : decoder_state := IDLE;

state_machine : process(clk, reset)
begin
    if reset = '1' then
        current_state <= IDLE;
    elsif rising_edge(clk) then
        case current_state is
            when IDLE =>
                if data_valid = '1' then
                    current_state <= DECODING;
                end if;

            when DECODING =>
                if error = '1' then
                    current_state <= ERROR_HANDLING;
                elsif data_valid = '0' then
                    current_state <= IDLE;
                end if;

            when ERROR_HANDLING =>
                if error_cleared = '1' then
                    current_state <= IDLE;
                end if;
        end case;
    end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity testbench_8b10b is
end testbench_8b10b;

architecture Behavioral of testbench_8b10b is
    component encoder_8b10b
        Port ( 
            clk : in STD_LOGIC;
            reset : in STD_LOGIC;
            data_in : in STD_LOGIC_VECTOR (7 downto 0);
            k_in : in STD_LOGIC;
            data_out : out STD_LOGIC_VECTOR (9 downto 0)
        );
    end component;

    component decoder_8b10b
        Port ( 
            clk : in STD_LOGIC;
            reset : in STD_LOGIC;
            data_in : in STD_LOGIC_VECTOR (9 downto 0);
            data_out : out STD_LOGIC_VECTOR (7 downto 0);
            k_out : out STD_LOGIC;
            error : out STD_LOGIC
        );
    end component;

    signal clk : STD_LOGIC := '0';
    signal reset : STD_LOGIC := '0';
    signal data_in_8b : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
    signal k_in : STD_LOGIC := '0';
    signal data_encoded : STD_LOGIC_VECTOR(9 downto 0);
    signal data_decoded : STD_LOGIC_VECTOR(7 downto 0);
    signal k_out : STD_LOGIC;
    signal error : STD_LOGIC;

    constant clk_period : time := 10 ns;

begin
    uut_encoder: encoder_8b10b
        port map (
            clk => clk,
            reset => reset,
            data_in => data_in_8b,
            k_in => k_in,
            data_out => data_encoded
        );

    uut_decoder: decoder_8b10b
        port map (
            clk => clk,
            reset => reset,
            data_in => data_encoded,
            data_out => data_decoded,
            k_out => k_out,
            error => error
        );

    clk_process: process
    begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
    end process;

    stim_proc: process
    begin
        reset <= '1';
        wait for clk_period*2;
        reset <= '0';

        -- テストケース1: 通常データ
        data_in_8b <= "10101010";
        k_in <= '0';
        wait for clk_period;

        -- テストケース2: 特殊文字
        data_in_8b <= "11111100";  -- K28.5
        k_in <= '1';
        wait for clk_period;

        -- テストケース3: ランニングディスパリティの変化を確認
        data_in_8b <= "00000000";
        k_in <= '0';
        wait for clk_period;
        data_in_8b <= "11111111";
        wait for clk_period;

        -- 追加のテストケース

        wait;
    end process;

end Behavioral;

-- 波形解析用の信号を追加
signal encoded_data_history : STD_LOGIC_VECTOR(29 downto 0);
signal decoded_data_history : STD_LOGIC_VECTOR(23 downto 0);

-- プロセスで信号の履歴を記録
process(clk)
begin
    if rising_edge(clk) then
        encoded_data_history <= encoded_data_history(19 downto 0) & data_encoded;
        decoded_data_history <= decoded_data_history(15 downto 0) & data_decoded;
    end if;
end process;

-- 波形ビューアで観察する信号
-- data_in_8b, k_in, data_encoded, data_decoded, k_out, error,
-- encoded_data_history, decoded_data_history

-- テストベンチのstim_procに追加
-- エッジケース1: 連続したゼロ
data_in_8b <= "00000000";
k_in <= '0';
wait for clk_period * 5;

-- エッジケース2: 連続したワン
data_in_8b <= "11111111";
k_in <= '0';
wait for clk_period * 5;

-- エッジケース3: 特殊文字の連続
data_in_8b <= "10111100";  -- K28.0
k_in <= '1';
wait for clk_period;
data_in_8b <= "10111100";  -- K28.0
k_in <= '1';
wait for clk_period;

-- エッジケース4: ランニングディスパリティの急激な変化
data_in_8b <= "00000000";
k_in <= '0';
wait for clk_period;
data_in_8b <= "11111111";
k_in <= '0';
wait for clk_period;
data_in_8b <= "00000000";
k_in <= '0';
wait for clk_period;

-- エッジケース5: 無効なコードワード（エラー検出のテスト）
data_encoded <= "1111111111";  -- 無効な10bコード
wait for clk_period;

-- パイプライン化の例
signal stage1_output, stage2_output : STD_LOGIC_VECTOR(9 downto 0);

process(clk)
begin
    if rising_edge(clk) then
        -- Stage 1
        stage1_output <= perform_5b6b_encoding(data_in(4 downto 0));

        -- Stage 2
        stage2_output <= stage1_output & perform_3b4b_encoding(data_in(7 downto 5));

        -- Final output
        data_out <= stage2_output;
    end if;
end process;

-- リソース共有の例
type encoding_table is array(0 to 31) of STD_LOGIC_VECTOR(5 downto 0);
constant encode_5b6b : encoding_table := (
    -- テーブルの内容
);

shared variable current_index : integer range 0 to 31;

process(clk)
begin
    if rising_edge(clk) then
        if encoding_5b6b then
            current_index := to_integer(unsigned(data_in(4 downto 0)));
        else
            current_index := to_integer(unsigned(data_in(7 downto 5))) + 24;
        end if;
        encoded_output <= encode_5b6b(current_index);
    end if;
end process;

-- タイミング制約の例（UCFファイル内）
NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 8 ns HIGH 50%;

-- 2段フリップフロップによる同期化
signal async_input : STD_LOGIC;
signal sync_stage1, sync_stage2 : STD_LOGIC;

process(clk)
begin
    if rising_edge(clk) then
        sync_stage1 <= async_input;
        sync_stage2 <= sync_stage1;
    end if;
end process;

-- ILAコアの例
component ila_0
    port (
        clk : in STD_LOGIC;
        probe0 : in STD_LOGIC_VECTOR(7 downto 0);
        probe1 : in STD_LOGIC_VECTOR(9 downto 0)
    );
end component;

-- ILAの接続
debug_ila : ila_0
    port map (
        clk => clk,
        probe0 => data_in,
        probe1 => data_encoded
    );

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity serial_interface is
    Port ( 
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        data_in : in STD_LOGIC_VECTOR(7 downto 0);
        data_valid : in STD_LOGIC;
        tx_out : out STD_LOGIC
    );
end serial_interface;

architecture Behavioral of serial_interface is
    component encoder_8b10b
        Port ( 
            clk : in STD_LOGIC;
            reset : in STD_LOGIC;
            data_in : in STD_LOGIC_VECTOR(7 downto 0);
            k_in : in STD_LOGIC;
            data_out : out STD_LOGIC_VECTOR(9 downto 0)
        );
    end component;

    signal encoded_data : STD_LOGIC_VECTOR(9 downto 0);
    signal shift_reg : STD_LOGIC_VECTOR(9 downto 0);
    signal bit_counter : integer range 0 to 9 := 0;
    signal k_in : STD_LOGIC := '0';

begin
    encoder : encoder_8b10b
        port map (
            clk => clk,
            reset => reset,
            data_in => data_in,
            k_in => k_in,
            data_out => encoded_data
        );

    process(clk, reset)
    begin
        if reset = '1' then
            shift_reg <= (others => '0');
            bit_counter <= 0;
            tx_out <= '1';
        elsif rising_edge(clk) then
            if data_valid = '1' then
                shift_reg <= encoded_data;
                bit_counter <= 0;
            elsif bit_counter < 10 then
                tx_out <= shift_reg(0);
                shift_reg <= '0' & shift_reg(9 downto 1);
                bit_counter <= bit_counter + 1;
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity storage_controller is
    Port ( 
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        write_data : in STD_LOGIC_VECTOR(7 downto 0);
        write_en : in STD_LOGIC;
        read_data : out STD_LOGIC_VECTOR(7 downto 0);
        read_en : in STD_LOGIC;
        storage_out : out STD_LOGIC;
        storage_in : in STD_LOGIC
    );
end storage_controller;

architecture Behavioral of storage_controller is
    component encoder_8b10b
        Port ( 
            clk : in STD_LOGIC;
            reset : in STD_LOGIC;
            data_in : in STD_LOGIC_VECTOR(7 downto 0);
            k_in : in STD_LOGIC;
            data_out : out STD_LOGIC_VECTOR(9 downto 0)
        );
    end component;

    component decoder_8b10b
        Port ( 
            clk : in STD_LOGIC;
            reset : in STD_LOGIC;
            data_in : in STD_LOGIC_VECTOR(9 downto 0);
            data_out : out STD_LOGIC_VECTOR(7 downto 0);
            k_out : out STD_LOGIC;
            error : out STD_LOGIC
        );
    end component;

    signal encoded_data : STD_LOGIC_VECTOR(9 downto 0);
    signal decoded_data : STD_LOGIC_VECTOR(7 downto 0);
    signal write_shift_reg : STD_LOGIC_VECTOR(9 downto 0);
    signal read_shift_reg : STD_LOGIC_VECTOR(9 downto 0);
    signal bit_counter : integer range 0 to 9 := 0;
    signal k_in, k_out, error : STD_LOGIC := '0';

begin
    encoder : encoder_8b10b
        port map (
            clk => clk,
            reset => reset,
            data_in => write_data,
            k_in => k_in,
            data_out => encoded_data
        );

    decoder : decoder_8b10b
        port map (
            clk => clk,
            reset => reset,
            data_in => read_shift_reg,
            data_out => decoded_data,
            k_out => k_out,
            error => error
        );

    process(clk, reset)
    begin
        if reset = '1' then
            write_shift_reg <= (others => '0');
            read_shift_reg <= (others => '0');
            bit_counter <= 0;
            storage_out <= '1';
        elsif rising_edge(clk) then
            if write_en = '1' then
                write_shift_reg <= encoded_data;
                bit_counter <= 0;
            elsif read_en = '1' then
                read_shift_reg <= read_shift_reg(8 downto 0) & storage_in;
                bit_counter <= bit_counter + 1;
                if bit_counter = 9 then
                    read_data <= decoded_data;
                    bit_counter <= 0;
                end if;
            elsif bit_counter < 10 then
                storage_out <= write_shift_reg(0);
                write_shift_reg <= '0' & write_shift_reg(9 downto 1);
                bit_counter <= bit_counter + 1;
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fpga_8b10b_system is
    Port ( 
        clk : in STD_LOGIC;
        reset : in STD_LOGIC;
        sw : in STD_LOGIC_VECTOR(7 downto 0);
        btn : in STD_LOGIC_VECTOR(3 downto 0);
        led : out STD_LOGIC_VECTOR(7 downto 0);
        uart_tx : out STD_LOGIC;
        uart_rx : in STD_LOGIC
    );
end fpga_8b10b_system;

architecture Behavioral of fpga_8b10b_system is
    component serial_interface
        Port ( 
            clk : in STD_LOGIC;
            reset : in STD_LOGIC;
            data_in : in STD_LOGIC_VECTOR(7 downto 0);
            data_valid : in STD_LOGIC;
            tx_out : out STD_LOGIC
        );
    end component;

    component storage_controller
        Port ( 
            clk : in STD_LOGIC;
            reset : in STD_LOGIC;
            write_data : in STD_LOGIC_VECTOR(7 downto 0);
            write_en : in STD_LOGIC;
            read_data : out STD_LOGIC_VECTOR(7 downto 0);
            read_en : in STD_LOGIC;
            storage_out : out STD_LOGIC;
            storage_in : in STD_LOGIC
        );
    end component;

    signal internal_data : STD_LOGIC_VECTOR(7 downto 0);
    signal data_valid, write_en, read_en : STD_LOGIC;
    signal storage_data : STD_LOGIC;

begin
    serial_if : serial_interface
        port map (
            clk => clk,
            reset => reset,
            data_in => sw,
            data_valid => data_valid,
            tx_out => uart_tx
        );

    storage_ctrl : storage_controller
        port map (
            clk => clk,
            reset => reset,
            write_data => sw,
            write_en => write_en,
            read_data => internal_data,
            read_en => read_en,
            storage_out => storage_data,
            storage_in => uart_rx
        );

    process(clk, reset)
    begin
        if reset = '1' then
            led <= (others => '0');
            data_valid <= '0';
            write_en <= '0';
            read_en <= '0';
        elsif rising_edge(clk) then
            data_valid <= btn(0);
            write_en <= btn(1);
            read_en <= btn(2);
            if btn(3) = '1' then
                led <= internal_data;
            else
                led <= sw;
            end if;
        end if;
    end process;
end Behavioral;