VHDLにおける連接演算子の基礎知識と活用16選

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity concatenation_example is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           c : out STD_LOGIC_VECTOR (7 downto 0));
end concatenation_example;

architecture Behavioral of concatenation_example is
begin
    c <= a & b;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity basic_concatenation is
    Port ( input1 : in  STD_LOGIC_VECTOR (3 downto 0);
           input2 : in  STD_LOGIC_VECTOR (3 downto 0);
           control : in  STD_LOGIC;
           output : out STD_LOGIC_VECTOR (8 downto 0));
end basic_concatenation;

architecture Behavioral of basic_concatenation is
    signal intermediate : STD_LOGIC_VECTOR (7 downto 0);
begin
    intermediate <= input1 & input2;
    output <= control & intermediate;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity signal_concatenation is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (7 downto 0);
           data_out : out STD_LOGIC_VECTOR (15 downto 0));
end signal_concatenation;

architecture Behavioral of signal_concatenation is
    signal counter : UNSIGNED (3 downto 0) := (others => '0');
    signal stored_data : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
            stored_data <= (others => '0');
        elsif rising_edge(clk) then
            counter <= counter + 1;
            stored_data <= data_in;
        end if;
    end process;

    data_out <= std_logic_vector(counter) & stored_data & data_in;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bit_manipulation is
    Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);
           b : in  STD_LOGIC_VECTOR (3 downto 0);
           c : in  STD_LOGIC_VECTOR (1 downto 0);
           result : out STD_LOGIC_VECTOR (9 downto 0));
end bit_manipulation;

architecture Behavioral of bit_manipulation is
begin
    result <= a & b & c;

    process(a, b, c)
        variable temp : STD_LOGIC_VECTOR (9 downto 0);
    begin
        temp := a & b & c;
        -- 特定のビットを抽出
        report "最上位4ビット: " & to_string(temp(9 downto 6));
        report "中間4ビット: " & to_string(temp(5 downto 2));
        report "最下位2ビット: " & to_string(temp(1 downto 0));
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bit_inversion is
    Port ( input : in  STD_LOGIC_VECTOR (7 downto 0);
           output : out STD_LOGIC_VECTOR (7 downto 0));
end bit_inversion;

architecture Behavioral of bit_inversion is
begin
    output <= not input(3 downto 0) & not input(7 downto 4);

    process(input)
    begin
        report "入力: " & to_string(input);
        report "出力: " & to_string(not input(3 downto 0) & not input(7 downto 4));
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity dynamic_width is
    Port ( input : in  STD_LOGIC_VECTOR (7 downto 0);
           width : in  INTEGER range 1 to 16;
           output : out STD_LOGIC_VECTOR (15 downto 0));
end dynamic_width;

architecture Behavioral of dynamic_width is
begin
    process(input, width)
        variable temp : STD_LOGIC_VECTOR (15 downto 0);
    begin
        if width <= 8 then
            -- ビット幅を縮小
            temp := (others => '0');
            temp(width-1 downto 0) := input(width-1 downto 0);
        else
            -- ビット幅を拡張
            temp := (others => '0');
            temp(7 downto 0) := input;
            temp(width-1 downto 8) := (others => input(7));  -- 符号拡張
        end if;
        output <= temp;

        report "入力: " & to_string(input);
        report "指定幅: " & integer'image(width);
        report "出力: " & to_string(temp);
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity padding_truncation is
    Port ( input : in  STD_LOGIC_VECTOR (7 downto 0);
           padded : out STD_LOGIC_VECTOR (15 downto 0);
           truncated : out STD_LOGIC_VECTOR (3 downto 0));
end padding_truncation;

architecture Behavioral of padding_truncation is
begin
    -- ゼロパディング
    padded <= "00000000" & input;

    -- トランケーション
    truncated <= input(3 downto 0);

    process(input)
    begin
        report "入力: " & to_string(input);
        report "パディング後: " & to_string("00000000" & input);
        report "トランケーション後: " & to_string(input(3 downto 0));
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity efficient_mux is
    Port ( inputs : in  STD_LOGIC_VECTOR (15 downto 0);
           sel : in  STD_LOGIC_VECTOR (1 downto 0);
           output : out STD_LOGIC_VECTOR (3 downto 0));
end efficient_mux;

architecture Behavioral of efficient_mux is
begin
    output <= inputs(to_integer(unsigned(sel))*4+3 downto to_integer(unsigned(sel))*4);

    process(inputs, sel)
    begin
        report "入力: " & to_string(inputs);
        report "選択信号: " & to_string(sel);
        report "出力: " & to_string(inputs(to_integer(unsigned(sel))*4+3 downto to_integer(unsigned(sel))*4));
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity optimized_arithmetic is
    Port ( a : in  STD_LOGIC_VECTOR (7 downto 0);
           b : in  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
           sum : out STD_LOGIC_VECTOR (8 downto 0);
           counter : out STD_LOGIC_VECTOR (3 downto 0));
end optimized_arithmetic;

architecture Behavioral of optimized_arithmetic is
    signal count : UNSIGNED (3 downto 0) := (others => '0');
begin
    -- 加算器
    sum <= std_logic_vector('0' & unsigned(a) + unsigned(b));

    -- カウンター
    process(clk)
    begin
        if rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;

    counter <= std_logic_vector(count);

    process(a, b, count)
    begin
        report "a: " & to_string(a);
        report "b: " & to_string(b);
        report "合計: " & to_string(std_logic_vector('0' & unsigned(a) + unsigned(b)));
        report "カウンター値: " & to_string(std_logic_vector(count));
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity parity_checker is
    Port ( data : in  STD_LOGIC_VECTOR (7 downto 0);
           parity : out STD_LOGIC);
end parity_checker;

architecture Behavioral of parity_checker is
begin
    parity <= xor data;

    process(data)
        variable parity_calc : STD_LOGIC;
    begin
        parity_calc := '0';
        for i in data'range loop
            parity_calc := parity_calc xor data(i);
        end process;
        report "入力データ: " & to_string(data);
        report "計算されたパリティ: " & std_logic'image(parity_calc);
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity barrel_shifter is
    Port ( data : in  STD_LOGIC_VECTOR (7 downto 0);
           shift : in  STD_LOGIC_VECTOR (2 downto 0);
           direction : in  STD_LOGIC;  -- '0' for left, '1' for right
           result : out STD_LOGIC_VECTOR (7 downto 0));
end barrel_shifter;

architecture Behavioral of barrel_shifter is
begin
    process(data, shift, direction)
        variable shift_amount : INTEGER;
        variable shifted_data : STD_LOGIC_VECTOR (7 downto 0);
    begin
        shift_amount := to_integer(unsigned(shift));

        if direction = '0' then
            -- 左シフト
            shifted_data := data(7-shift_amount downto 0) & (shift_amount-1 downto 0 => '0');
        else
            -- 右シフト
            shifted_data := (7 downto 8-shift_amount => '0') & data(7 downto shift_amount);
        end if;

        result <= shifted_data;

        report "入力データ: " & to_string(data);
        report "シフト量: " & integer'image(shift_amount);
        report "シフト方向: " & (if direction = '0' then "左" else "右");
        report "シフト後のデータ: " & to_string(shifted_data);
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity type_mismatch_example is
    Port ( a : in  STD_LOGIC;
           b : in  STD_LOGIC_VECTOR(2 downto 0);
           c : out STD_LOGIC_VECTOR(3 downto 0));
end type_mismatch_example;

architecture Behavioral of type_mismatch_example is
begin
    -- エラーを引き起こすコード
    -- c <= a & b;  -- 型の不一致によりエラー

    -- 正しいコード
    c <= std_logic_vector'(a) & b;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity bit_width_mismatch_example is
    Port ( a : in  STD_LOGIC_VECTOR(7 downto 0);
           b : in  STD_LOGIC_VECTOR(3 downto 0);
           c : out STD_LOGIC_VECTOR(15 downto 0));
end bit_width_mismatch_example;

architecture Behavioral of bit_width_mismatch_example is
begin
    -- ビット幅を明示的に指定
    c <= std_logic_vector(resize(unsigned(a), 12)) & b;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity timing_improvement_example is
    Port ( clk : in  STD_LOGIC;
           a, b, c, d : in  STD_LOGIC_VECTOR(7 downto 0);
           result : out STD_LOGIC_VECTOR(31 downto 0));
end timing_improvement_example;

architecture Behavioral of timing_improvement_example is
    signal intermediate1, intermediate2 : STD_LOGIC_VECTOR(15 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            -- 段階的に連接を行い、タイミングを改善
            intermediate1 <= a & b;
            intermediate2 <= c & d;
            result <= intermediate1 & intermediate2;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity variable_length_encoder is
    Port ( data : in  STD_LOGIC_VECTOR(7 downto 0);
           length : in  STD_LOGIC_VECTOR(2 downto 0);
           encoded : out STD_LOGIC_VECTOR(15 downto 0);
           valid : out STD_LOGIC);
end variable_length_encoder;

architecture Behavioral of variable_length_encoder is
begin
    process(data, length)
        variable temp : STD_LOGIC_VECTOR(15 downto 0);
        variable len : INTEGER;
    begin
        len := to_integer(unsigned(length));
        temp := (others => '0');
        temp(len-1 downto 0) := data(len-1 downto 0);

        -- エンコードされたデータを生成
        encoded <= "1111111100000000" & temp(7 downto 0);

        -- 有効ビットを設定
        valid <= '1' when len > 0 and len <= 8 else '0';
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity crc_generator is
    Port ( data : in  STD_LOGIC_VECTOR(7 downto 0);
           crc_in : in  STD_LOGIC_VECTOR(15 downto 0);
           crc_out : out STD_LOGIC_VECTOR(15 downto 0));
end crc_generator;

architecture Behavioral of crc_generator is
    function update_crc(data : STD_LOGIC_VECTOR(7 downto 0); 
                        crc : STD_LOGIC_VECTOR(15 downto 0)) 
                        return STD_LOGIC_VECTOR is
        variable new_crc : STD_LOGIC_VECTOR(15 downto 0);
    begin
        new_crc := crc;
        for i in 0 to 7 loop
            if (new_crc(15) xor data(i)) = '1' then
                new_crc := (new_crc(14 downto 0) & '0') xor x"1021";
            else
                new_crc := new_crc(14 downto 0) & '0';
            end if;
        end process;
        return new_crc;
    end function;

begin
    crc_out <= update_crc(data, crc_in);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity optimized_datapath is
    Port ( a, b : in  STD_LOGIC_VECTOR(7 downto 0);
           opcode : in  STD_LOGIC_VECTOR(2 downto 0);
           result : out STD_LOGIC_VECTOR(15 downto 0));
end optimized_datapath;

architecture Behavioral of optimized_datapath is
    signal add_result, sub_result : STD_LOGIC_VECTOR(8 downto 0);
    signal mult_result : STD_LOGIC_VECTOR(15 downto 0);
begin
    add_result <= std_logic_vector(unsigned('0' & a) + unsigned('0' & b));
    sub_result <= std_logic_vector(unsigned('0' & a) - unsigned('0' & b));
    mult_result <= std_logic_vector(unsigned(a) * unsigned(b));

    with opcode select
        result <= "0000000" & add_result when "000",
                  "0000000" & sub_result when "001",
                  mult_result when "010",
                  (others => '0') when others;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity custom_alu is
    Port ( a, b : in  STD_LOGIC_VECTOR(7 downto 0);
           op : in  STD_LOGIC_VECTOR(3 downto 0);
           result : out STD_LOGIC_VECTOR(15 downto 0);
           flags : out STD_LOGIC_VECTOR(3 downto 0)); -- Zero, Carry, Negative, Overflow
end custom_alu;

architecture Behavioral of custom_alu is
    signal temp_result : STD_LOGIC_VECTOR(15 downto 0);
    signal carry : STD_LOGIC;
begin
    process(a, b, op)
        variable unsigned_a, unsigned_b : UNSIGNED(7 downto 0);
        variable signed_a, signed_b : SIGNED(7 downto 0);
    begin
        unsigned_a := UNSIGNED(a);
        unsigned_b := UNSIGNED(b);
        signed_a := SIGNED(a);
        signed_b := SIGNED(b);

        case op is
            when "0000" => -- 加算
                temp_result <= STD_LOGIC_VECTOR(RESIZE(unsigned_a + unsigned_b, 16));
                carry <= '1' when (unsigned_a + unsigned_b) > 255 else '0';
            when "0001" => -- 減算
                temp_result <= STD_LOGIC_VECTOR(RESIZE(unsigned_a - unsigned_b, 16));
                carry <= '1' when unsigned_a < unsigned_b else '0';
            when "0010" => -- 論理AND
                temp_result <= "00000000" & (a and b);
                carry <= '0';
            when "0011" => -- 論理OR
                temp_result <= "00000000" & (a or b);
                carry <= '0';
            when "0100" => -- 論理XOR
                temp_result <= "00000000" & (a xor b);
                carry <= '0';
            when "0101" => -- 左シフト
                temp_result <= STD_LOGIC_VECTOR(SHIFT_LEFT(RESIZE(unsigned_a, 16), TO_INTEGER(unsigned_b)));
                carry <= a(7-TO_INTEGER(unsigned_b)+1) when TO_INTEGER(unsigned_b) > 0 and TO_INTEGER(unsigned_b) <= 8 else '0';
            when "0110" => -- 右シフト
                temp_result <= "00000000" & STD_LOGIC_VECTOR(SHIFT_RIGHT(unsigned_a, TO_INTEGER(unsigned_b)));
                carry <= a(TO_INTEGER(unsigned_b)-1) when TO_INTEGER(unsigned_b) > 0 and TO_INTEGER(unsigned_b) <= 8 else '0';
            when others =>
                temp_result <= (others => '0');
                carry <= '0';
        end case;
    end process;

    result <= temp_result;
    flags <= temp_result(15 downto 15) & -- Negative
             carry &                     -- Carry
             (temp_result(7 downto 0) = "00000000") & -- Zero
             '0';                        -- Overflow (未実装)
end Behavioral;