VHDLでの整数操作を習得！実践サンプルコード10選

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity integer_example is
end entity integer_example;

architecture behavior of integer_example is
  signal my_integer : integer := 10;
begin
  process
  begin
    report integer'image(my_integer);
    wait;
  end process;
end behavior;

-- 上部のライブラリ宣言などは省略
architecture behavior of integer_example is
  signal a, b, sum_result, sub_result : integer := 0;
begin
  process
  begin
    a <= 15;
    b <= 5;
    sum_result <= a + b;
    sub_result <= a - b;
    report "Sum: " & integer'image(sum_result);
    report "Sub: " & integer'image(sub_result);
    wait;
  end process;
end behavior;

-- 乗算と除算のサンプルコード
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity multiply_and_divide is
    Port ( A : in  integer := 8;   -- 入力整数A
           B : in  integer := 4;   -- 入力整数B
           Mul : out integer;      -- 乗算結果
           Div : out integer);     -- 除算結果
end multiply_and_divide;

architecture Behavior of multiply_and_divide is
begin
    Mul <= A * B;  -- 乗算の操作
    Div <= A / B;  -- 除算の操作
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity range_example is
end range_example;

architecture Behavioral of range_example is
    signal integer_value: integer range 10 to 50 := 30;
begin
    process
    begin
        report "整数の値: " & integer'image(integer_value);
        wait;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity range_handle_example is
end range_handle_example;

architecture Behavioral of range_handle_example is
    signal integer_value: integer := 55;
begin
    process
    begin
        if integer_value < 10 or integer_value > 50 then
            report "エラー: 範囲外の値が入力されました";
        else
            report "整数の値: " & integer'image(integer_value);
        end if;
        wait;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bit_shift is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_in : in INTEGER;
           left_shift_out : out INTEGER;
           right_shift_out : out INTEGER);
end bit_shift;

architecture Behavior of bit_shift is
begin
    process(clk, rst)
    begin
        -- クロックが上昇エッジのとき
        if rising_edge(clk) then
            if rst = '1' then
                -- リセットがアクティブなら、シフト結果を0にする
                left_shift_out <= 0;
                right_shift_out <= 0;
            else
                -- 左に2ビットシフト
                left_shift_out <= data_in * 4;
                -- 右に2ビットシフト
                right_shift_out <= data_in / 4;
            end if;
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity int_compare is
    Port ( data1 : in INTEGER;
           data2 : in INTEGER;
           result : out INTEGER);
end int_compare;

architecture Behavior of int_compare is
begin
    process(data1, data2)
    begin
        if data1 > data2 then
            result <= 1;
        elsif data1 = data2 then
            result <= 0;
        else
            result <= -1;
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity int_loop is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_in : in INTEGER;
           result : out INTEGER);
end int_loop;

architecture Behavior of int_loop is
    signal temp_result : INTEGER := 0;
begin
    process(clk, rst)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                temp_result <= 0;
            else
                for i in 1 to data_in loop
                    temp_result <= temp_result + 1;
                end loop;
                result <= temp_result;
            end if;
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_integer is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_array : in array(0 to 4) of INTEGER;
           sum : out INTEGER);
end array_integer;

architecture Behavior of array_integer is
    signal temp_sum : INTEGER := 0;
begin
    process(clk, rst)
    begin
        if rising_edge(clk) then
            if rst = '1' then
                temp_sum <= 0;
            else
                temp_sum <= 0; -- 初期化
                for i in 0 to 4 loop
                    temp_sum <= temp_sum + data_array(i);
                end loop;
                sum <= temp_sum;
            end if;
        end if;
    end process;
end Behavior;

vhdl
function max_value(a : integer; b : integer) return integer is
begin
    if a > b then
        return a;
    else
        return b;
    end if;
end function max_value;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cast_example is
    Port ( input_data : in STD_LOGIC_VECTOR(7 downto 0);
           output_data : out INTEGER);
end cast_example;

architecture Behavior of cast_example is
begin
    process(input_data)
    begin
        output_data <= conv_integer(input_data);
    end process;
end Behavior;

function 関数名(引数) return 戻り値の型 is
begin
    -- 処理内容
end function 関数名;