VHDL内部信号を完全マスター！10のサンプルコードを徹底解説！

entity sample1 is
    port(a, b : in std_logic_vector(3 downto 0);
         sum : out std_logic_vector(3 downto 0));
end entity sample1;

architecture behavior of sample1 is
    signal internal_sum : std_logic_vector(3 downto 0);
begin
    internal_sum <= a + b;
    sum <= internal_sum;
end architecture behavior;

entity sample2 is
    port(a, b : in std_logic_vector(3 downto 0);
         sum, diff : out std_logic_vector(3 downto 0));
end entity sample2;

architecture behavior of sample2 is
    signal internal_sum, internal_diff : std_logic_vector(3 downto 0);
begin
    internal_sum <= a + b;
    internal_diff <= a - b;

    sum <= internal_sum;
    diff <= internal_diff;
end architecture behavior;

entity sample3 is
    port(a, b : in std_logic_vector(3 downto 0);
         select : in std_logic;
         result : out std_logic_vector(3 downto 0));
end entity sample3;

architecture behavior of sample3 is
    signal internal_res : std_logic_vector(3 downto 0);
begin
    process(a, b, select)
    begin
        if select = '1' then
            internal_res <= a + b;
        else
            internal_res <= a - b;
        end if;
    end process;

    result <= internal_res;
end architecture behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Arithmetic is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           Add_result : out  STD_LOGIC_VECTOR (7 downto 0);
           Subtract_result : out  STD_LOGIC_VECTOR (7 downto 0));
end Arithmetic;

architecture Behavior of Arithmetic is
    signal temp_add : STD_LOGIC_VECTOR (7 downto 0);
    signal temp_sub : STD_LOGIC_VECTOR (7 downto 0);
begin
    temp_add <= A + B;            -- 加算
    temp_sub <= A - B;            -- 減算

    Add_result <= temp_add;
    Subtract_result <= temp_sub;
end Behavior;

-- (略) 必要なライブラリとパッケージのインクルード

entity Bin2Dec is
    Port ( Bin : in STD_LOGIC_VECTOR(3 downto 0);
           Dec : out INTEGER RANGE 0 to 15);
end Bin2Dec;

architecture Behavior of Bin2Dec is
begin
    process(Bin)
    begin
        Dec <= CONV_INTEGER(Bin);
    end process;
end Behavior;

-- (略) 必要なライブラリとパッケージのインクルード

entity ConditionOutput is
    Port ( A : in INTEGER RANGE 0 to 15;
           B : in STD_LOGIC_VECTOR(3 downto 0);
           Out : out STD_LOGIC_VECTOR(3 downto 0));
end ConditionOutput;

architecture Behavior of ConditionOutput is
begin
    process(A, B)
    begin
        if A >= 10 then
            Out <= B;
        else
            Out <= (others => '0');
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity FanControl is
    Port ( Temp : in  STD_LOGIC_VECTOR(7 downto 0);
           Fan : out STD_LOGIC);
end FanControl;

architecture Behavior of FanControl is
    signal threshold : STD_LOGIC_VECTOR(7 downto 0) := "01011010"; -- 90度を表す値
begin
    process(Temp)
    begin
        if Temp > threshold then
            Fan <= '1'; -- 温度が90度を超えた場合、冷却ファンを起動
        else
            Fan <= '0'; -- それ以外の場合は、冷却ファンを停止
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity EnhancedFanControl is
    Port ( Temp : in  STD_LOGIC_VECTOR(7 downto 0);
           Fan : out STD_LOGIC;
           Alert : out STD_LOGIC);
end EnhancedFanControl;

architecture Behavior of EnhancedFanControl is
    signal threshold : STD_LOGIC_VECTOR(7 downto 0) := "01011010"; -- 90度を示す値
    signal alert_threshold : STD_LOGIC_VECTOR(7 downto 0) := "10100000"; -- 160度を示す値
begin
    process(Temp)
    begin
        if Temp > alert_threshold then
            Alert <= '1'; -- 温度が160度を超えた場合、警告信号を出力
        else
            Alert <= '0';
        end if;

        if Temp > threshold then
            Fan <= '1'; -- 温度が90度を超えた場合、冷却ファンを起動
        else
            Fan <= '0';
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ComplexLogic is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : out STD_LOGIC);
end ComplexLogic;

architecture Behavioral of ComplexLogic is
    signal inter_signal1 : STD_LOGIC;
    signal inter_signal2 : STD_LOGIC;
begin
    -- 以下のコードでは、AとBの入力に基づいて内部信号を操作しています。
    inter_signal1 <= A AND B;
    inter_signal2 <= A OR B;

    -- この例では、inter_signal1とinter_signal2を使ってCの出力を生成します。
    C <= inter_signal1 XOR inter_signal2;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testbench is
end testbench;

architecture sim of testbench is
    signal internal_signal: std_logic;
    signal input_signal: std_logic := '0';
    signal output_signal: std_logic;

begin

    -- テスト対象の回路のインスタンス化
    UUT: entity work.target_circuit
    port map (
        input => input_signal,
        internal => internal_signal,
        output => output_signal
    );

    -- シミュレーションを制御するプロセス
    stimulus: process
    begin
        wait for 10 ns;
        input_signal <= '1';
        wait for 10 ns;
        input_signal <= '0';
        wait;
    end process stimulus;

end sim;

-- シミュレーションを制御するプロセス（応用例）
stimulus_advanced: process
begin
    wait for 5 ns;
    input_signal <= '1';
    wait for 20 ns;
    input_signal <= '0';
    wait for 15 ns;
    input_signal <= '1';
    wait;
end process stimulus_advanced;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DebugOptimize is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
       B : out STD_LOGIC_VECTOR (7 downto 0));
end DebugOptimize;

architecture Behavioral of DebugOptimize is
signal internal_signal: STD_LOGIC_VECTOR (7 downto 0); -- 内部信号の宣言
begin
process(A)
begin
    -- 何らかの処理
    internal_signal <= A + "00000001"; -- 例として、1を加算
end process;

B <= internal_signal; -- 内部信号を出力に接続

end Behavioral;

process(A)
begin
    if A = "00000000" then
        internal_signal <= A + "00000010";
    else
        internal_signal <= A + "00000001";
    end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
end test;

architecture behavior of test is
    signal signal_value: std_logic;
begin
    process_1: process
    begin
        -- プロセス1での内部信号の更新
        signal_value <= '1';
        wait for 10 ns;
    end process process_1;

    process_2: process
    begin
        -- プロセス2での内部信号の更新
        signal_value <= '0';
        wait for 10 ns;
    end process process_2;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity deadlock_example is
end deadlock_example;

architecture behavior of deadlock_example is
    signal signal_a, signal_b: std_logic := '0';
begin
    process_A: process(signal_a)
    begin
        if signal_a = '1' then
            signal_b <= '1';
        end if;
    end process process_A;

    process_B: process(signal_b)
    begin
        if signal_b = '1' then
            signal_a <= '1';
        end if;
    end process process_B;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- カスタムデータ型の定義
type my_data_type is array (7 downto 0) of std_logic_vector(3 downto 0);

-- 内部信号の定義
signal my_signal : my_data_type;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- 内部信号の定義
signal dynamic_signal : std_logic_vector(7 downto 0) := "00000000";

begin
  process
  begin
    wait for 10 ns;
    dynamic_signal <= "00000001";
    wait for 10 ns;
    dynamic_signal <= "00000010";
    wait for 10 ns;
    dynamic_signal <= "00000011";
  end process;