VHDLとnumeric_stdを初心者も使いこなせる10の手法

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Adder is
    Port ( A : in  signed(7 downto 0);
           B : in  signed(7 downto 0);
           Sum : out  signed(7 downto 0));
end Adder;

architecture Behavioral of Adder is
begin
    Sum <= A + B;
end Behavioral;

library IEEE;
use IEEE.numeric_std.all;

entity BasicCalc is
end BasicCalc;

architecture Behavior of BasicCalc is
    signal a, b, result : signed(7 downto 0);
begin
    a <= "00000101"; -- 5を二進数で表現
    b <= "00000011"; -- 3を二進数で表現

    -- 足し算の処理
    process
    begin
        result <= a + b;
        wait;
    end process;
end Behavior;

library IEEE;
use IEEE.numeric_std.all;

entity SignalManage is
end SignalManage;

architecture Behavior of SignalManage is
    signal count : signed(7 downto 0) := "00000000";
begin
    -- カウンタの処理
    process
    begin
        count <= count + 1;
        wait for 10 ns;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity complex_arith is
    Port ( A : in  STD_LOGIC_VECTOR(15 downto 0);
           B : in  STD_LOGIC_VECTOR(15 downto 0);
           Div : out  STD_LOGIC_VECTOR(15 downto 0);
           Mul : out  STD_LOGIC_VECTOR(31 downto 0));
end complex_arith;

architecture Behave of complex_arith is
    signal a_signed : signed(15 downto 0);
    signal b_signed : signed(15 downto 0);
begin

    -- 数値をsigned型に変換
    a_signed <= signed(A);
    b_signed <= signed(B);

    process(A, B)
    begin
        -- 割り算と乗算の演算
        Div <= std_logic_vector(a_signed / b_signed);
        Mul <= std_logic_vector(a_signed * b_signed);
    end process;

end Behave;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity simple_counter is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           count : out unsigned(7 downto 0));
end simple_counter;

architecture Behavior of simple_counter is
    signal tmp_count : unsigned(7 downto 0) := "00000000";
begin
    process(clk, rst)
    begin
        -- リセット処理
        if rst = '1' then
            tmp_count <= "00000000";
        -- クロックの立ち上がりエッジでカウントアップ
        elsif rising_edge(clk) then
            tmp_count <= tmp_count + 1;
        end if;
    end process;
    count <= tmp_count;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity memory_controller is
    Port ( clk : in STD_LOGIC;
           wr_en : in STD_LOGIC;
           rd_en : in STD_LOGIC;
           addr : in unsigned(7 downto 0);
           data_in : in unsigned(7 downto 0);
           data_out : out unsigned(7 downto 0));
end memory_controller;

architecture Behavior of memory_controller is
    type memory_array is array (0 to 255) of unsigned(7 downto 0);
    signal mem : memory_array := (others => "00000000");
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if wr_en = '1' then
                mem(to_integer(addr)) <= data_in;
            end if;
            if rd_en = '1' then
                data_out <= mem(to_integer(addr));
            end if;
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity condition_demo is
    Port ( input1 : in unsigned(3 downto 0);
           input2 : in unsigned(3 downto 0);
           operator : in STD_LOGIC_VECTOR(1 downto 0);
           result : out unsigned(3 downto 0));
end condition_demo;

architecture Behavior of condition_demo is
begin
    process(input1, input2, operator)
    begin
        -- 00: add, 01: subtract, 10: multiply, 11: divide
        case operator is
            when "00" =>
                result <= input1 + input2;
            when "01" =>
                result <= input1 - input2;
            when "10" =>
                result <= input1 * input2;
            when "11" =>
                if input2 /= 0 then
                    result <= input1 / input2;
                else
                    result <= "0000";
                end if;
            when others =>
                result <= "0000";
        end case;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity select_demo is
    Port ( input_val : in STD_LOGIC_VECTOR(3 downto 0);
           selected_operation : in STD_LOGIC_VECTOR(1 downto 0);
           output_val : out unsigned(3 downto 0));
end select_demo;

architecture Behavior of select_demo is
begin
    process(input_val, selected_operation)
    begin
        case selected_operation is
            when "00" =>
                output_val <= not to_unsigned(input_val, 4);
            when "01" =>
                output_val <= to_unsigned(input_val, 4) + 1;
            when "10" =>
                output_val <= to_unsigned(input_val, 4) - 1;
            when others =>
                output_val <= "0000";
        end case;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity EventDriven is
Port ( clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       out_signal : out STD_LOGIC);
end EventDriven;

architecture Behavior of EventDriven is
signal temp_signal : STD_LOGIC := '0';
begin
process(clk, rst)
begin
    -- リセット信号がアクティブならば
    if rst = '1' then
        temp_signal <= '0';
    -- クロックの立ち上がりエッジで
    elsif rising_edge(clk) then
        temp_signal <= not temp_signal;
    end if;
end process;

out_signal <= temp_signal;

end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;

entity data_conversion is
end entity data_conversion;

architecture Behavioral of data_conversion is
begin
    process
        variable num : integer := 10;  -- 変換したい数値
        variable str : string(1 to 4); -- 変換後の文字列を格納
    begin
        str := to_hexstring(to_unsigned(num, str'length * 4)); -- 数値を16進数の文字列に変換
        report "変換結果: " & str;  -- 結果を表示
        wait;
    end process;
end architecture Behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity error_handling is
  port(
    signal_value : in std_logic_vector(7 downto 0);
    ...
  );
end error_handling;

architecture behavior of error_handling is
begin
  process(signal_value)
  begin
    -- 信号の値が0x5A以外の場合に警告を出す
    assert signal_value /= "01011010"
    report "信号の値が不正です！" severity WARNING;
  end process;
end behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity overflow_check is
  port(
    A, B : in std_logic_vector(7 downto 0);
    SUM  : out std_logic_vector(7 downto 0);
    ...
  );
end overflow_check;

architecture behavior of overflow_check is
  signal sum_internal : unsigned(8 downto 0);
begin
  sum_internal <= unsigned(A) + unsigned(B);

  -- オーバーフローチェック
  assert sum_internal(8) = '0'
  report "加算結果

がオーバーフローしました！" severity ERROR;

  SUM <= std_logic_vector(sum_internal(7 downto 0));
end behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simulation_technique is
    port(
        A, B : in std_logic_vector(3 downto 0);
        SUM  : out std_logic_vector(4 downto 0)
    );
end simulation_technique;

architecture behavior of simulation_technique is
begin
    SUM <= std_logic_vector(unsigned(A) + unsigned(B));
end behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_simulation_technique is
end tb_simulation_technique;

architecture sim of tb_simulation_technique is
    signal A, B : std_logic_vector(3 downto 0);
    signal SUM  : std_logic_vector(4 downto 0);
    component simulation_technique
        port(
            A, B : in std_logic_vector(3 downto 0);
            SUM  : out std_logic_vector(4 downto 0)
        );
    end component;
begin
    DUT: simulation_technique port map(A, B, SUM);

    stim_proc: process
    begin
        A <= "0010"; B <= "0011"; wait for 10 ns;
        A <= "0100"; B <= "0111"; wait for 10 ns;
        A <= "1100"; B <= "1100"; wait for 10 ns;
        wait;
    end process;
end sim;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity data_type_problem is
end data_type_problem;

architecture sim of data_type_problem is
    signal a: std_logic_vector(7 downto 0);
    signal b: signed(7 downto 0);
    signal c: signed(7 downto 0);
begin
    -- aとbを足し合わせた結果をcに格納
    c <= b + signed(a);
end sim;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity overflow_example is
end overflow_example;

architecture sim of overflow_example is
    signal a: unsigned(7 downto 0) := "11111111";
    signal b: unsigned(7 downto 0) := "00000001";
    signal result: unsigned(7 downto 0);
begin
    result <= a + b;
end sim;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL; -- numeric_stdライブラリを使う場合
-- use 他のライブラリ; -- 他のライブラリを使う場合

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

function max_value(a: unsigned; b: unsigned) return unsigned is
begin
    if a > b then
        return a;
    else
        return b;
    end if;
end function max_value;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

package my_numeric is
    function bit_invert(data: unsigned) return unsigned;
end package my_numeric;

package body my_numeric is
    function bit_invert(data: unsigned) return unsigned is
        variable result: unsigned(data'range);
    begin
        for i in data'range loop
            result(i) := not data(i);
        end loop;
        return result;
    end function bit_invert;
end package body my_numeric;