VHDL初心者のためのNOW関数使い方10選

library IEEE;
use IEEE.std_logic_1164.ALL;

entity now_sample is
end now_sample;

architecture sim of now_sample is
begin
    process
    begin
        wait for 10 ns;
        report "現在のシミュレーション時刻は " & time'image(now) & " です。";
        wait;
    end process;
end sim;

library IEEE;
use IEEE.std_logic_1164.ALL;

entity now_sample2 is
end now_sample2;

architecture sim of now_sample2 is
    constant TARGET_TIME : time := 50 ns;
begin
    process
    begin
        wait until now > TARGET_TIME;
        report "指定時刻に到達しました。";
        wait;
    end process;
end sim;

library IEEE;
use IEEE.std_logic_1164.ALL;

entity now_timer is
end now_timer;

architecture sim of now_timer is
    constant INTERVAL : time := 10 ns;
begin
    process
    begin
        wait for INTERVAL;
        report "現在時刻：" & time'image(now);
    end process;
end sim;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;

entity NowFunctionSample is
end NowFunctionSample;

architecture sim of NowFunctionSample is
begin
    process
        variable line_var : LINE;
        variable time_string : STRING(1 to 30);
    begin
        wait for 10 ns;
        time_string := time'image(NOW);
        write(line_var, time_string);
        writeline(OUTPUT, line_var);
        wait;
    end process;
end sim;

-- サンプルコード5
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;

entity log_generator is
  -- ...
end log_generator;

architecture Behavioral of log_generator is
  -- ...
begin
  process
    variable log_line: LINE;
  begin
    wait until switch = '1';
    write(log_line, string'("操作時刻: " & NOW));
    writeline(output, log_line);
  end process;
end Behavioral;

-- サンプルコード6
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;

entity timer is
  -- ...
end timer;

architecture Behavioral of timer is
  signal start_time, end_time: TIME;
  -- ...
begin
  process
    variable time_difference: TIME;
    variable log_line: LINE;
  begin
    start_time <= NOW;
    -- 何らかの処理
    wait for 10 ns;
    end_time <= NOW;

    time_difference := end_time - start_time;
    write(log_line, string'("処理時間: " & time_difference));
    writeline(output, log_line);
  end process;
end Behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;

entity countdown is
-- こちらは端子の定義部分となります
end entity countdown;

architecture behavior of countdown is
begin
    process
        variable target_time : TIME := TO_TIME("2024-01-01 00:00:00");
        variable current_time : TIME;
        variable remaining_time : TIME;
    begin
        current_time := NOW;
        remaining_time := target_time - current_time;
        -- 以下で、残り時間を適切なフォーマットに変換して表示します。
    end process;
end architecture behavior;

-- 以下のライブラリとパッケージを使用します
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;

entity error_logger is
-- こちらは端子の定義部分となります
end entity error_logger;

architecture behavior of error_logger is
begin
    process
        variable error_occurred : BOOLEAN := false; -- エラーが発生したかを示す変数
    begin
        -- 何らかの条件でエラーが発生したとする
        error_occurred := true;

        if error_occurred then
            report "エラーが発生しました。時間：" & TIME_IMAGE(NOW);
        end if;
    end process;
end architecture behavior;

-- 必要なライブラリとパッケージを使用します
library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;

entity elapsed_time_display is
-- 端子の定義部分です


end entity elapsed_time_display;

architecture behavior of elapsed_time_display is
    variable start_time : TIME;
begin
    process
        variable elapsed : TIME;
    begin
        start_time := NOW; -- プロセス開始の時間を取得
        wait for 10 ns;   -- 何らかのプロセスを模擬
        elapsed := NOW - start_time;
        report "経過時間：" & TIME_IMAGE(elapsed);
    end process;
end architecture behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;

entity simple_calendar is
    port(
        clk : in std_logic; -- クロック信号
        reset : in std_logic; -- リセット信号
        date_time : out string(1 to 20) -- 日付と時間を表示する出力ポート
    );
end entity simple_calendar;

architecture behavior of simple_calendar is
begin
    process(clk, reset)
        variable current_time : TIME;
    begin
        if reset = '1' then
            date_time <= (others => ' '); -- リセット時は空白で初期化
        elsif rising_edge(clk) then
            current_time := NOW; 
            date_time <= "日付・時間：" & TIME_IMAGE(current_time); 
        end if;
    end process;
end architecture behavior;

library ieee;
use ieee.std_logic_1164.all;
use ieee.vital_timing.all;

entity high_precision_timer is
    port(
        ext_clk : in std_logic; -- 高精度の外部クロック信号
        timestamp : out string(1 to 20) -- タイムスタンプを表示する出力ポート
    );
end entity high_precision_timer;

architecture behavior of high_precision_timer is
begin
    process(ext_clk)
        variable precise_time : TIME;
    begin
        if rising_edge(ext_clk) then
            precise_time := NOW; 
            timestamp <= "時刻：" & TIME_IMAGE(precise_time); 
        end if;
    end process;
end architecture behavior;