VHDL減算入門！10の実践サンプルコードを紹介

-- このコードでは整数の減算を示しています。
-- この例では、10から5を引いて5という結果を得ています。
signal a, b, result : integer;
begin
    a <= 10;
    b <= 5;
    result <= a - b;  -- 減算の結果は5
end;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity basic_sub is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           C : out  STD_LOGIC_VECTOR(7 downto 0));
end basic_sub;

architecture Behavioral of basic_sub is
begin
    C <= A - B; -- AとBの差をCに代入
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bit_length_sub is
    Port ( X : in  STD_LOGIC_VECTOR(15 downto 0);
           Y : in  STD_LOGIC_VECTOR(7 downto 0);
           Z : out  STD_LOGIC_VECTOR(15 downto 0));
end bit_length_sub;

architecture Behavioral of bit_length_sub is
    signal Y_extended : STD_LOGIC_VECTOR(15 downto 0);
begin
    Y_extended <= "00000000" & Y; -- Yを16ビットに拡張
    Z <= X - Y_extended;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity overflow_sub is
    Port ( P : in  STD_LOGIC_VECTOR(7 downto 0);
           Q : in  STD_LOGIC_VECTOR(7 downto 0);
           R : out  STD_LOGIC_VECTOR(7 downto 0);
           error : out STD_LOGIC); -- オーバーフロー時に'1'を出力
end overflow_sub;

architecture Behavioral of overflow_sub is
begin
    process(P, Q)
    begin
        if P < Q then -- QがPより大きい場合、オーバーフローと判定
            error <= '1';
            R <= "00000000"; -- エラー時は0を出力
        else
            error <= '0';
            R <= P - Q;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity datatype_sub is
    Port ( S : in  STD_LOGIC_VECTOR(7 downto 0);
           T : in  integer range 0 to 255;
           U : out  STD_LOGIC_VECTOR(7 downto 0));
end datatype_sub;

architecture Behavioral of datatype_sub is
    signal T_vector : STD_LOGIC_VECTOR(7 downto 0);
begin
    T_vector <= conv_std_logic_vector(T, 8);  -- 整数型を8ビットのベクトルに変換
    U <= S - T_vector; 
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity signed_sub is
    Port ( V : in  STD_LOGIC_VECTOR(7 downto 0);
           W : in  signed(7 downto 0);
           X : out  STD_LOGIC_VECTOR(7 downto 0));
end signed_sub;

architecture Behavioral of signed_sub is
begin
    X <= conv_std_logic_vector(V - W, 8);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity countdown is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           count_val : out INTEGER RANGE 0 TO 100);
end countdown;

architecture Behavioral of countdown is
signal count : INTEGER RANGE 0 TO 100 := 100;
begin
process(clk, rst)
begin
    if rst = '1' then
        count <= 100;
    elsif rising_edge(clk) then
        if count > 0 then
            count <= count - 1;
        end if;
    end if;
end process;

count_val <= count;
end Behavioral;

-- 省略 --
signal value : INTEGER RANGE 0 TO 255 := 150;
signal correction : INTEGER RANGE -50 TO 50 := -10;

begin
process(clk)
begin
    if rising_edge(clk) then
        if value + correction >= 0 then
            value <= value + correction;
        else
            value <= 0;
        end if;
    end if;
end process;
-- 省略 --

-- 省略 --
signal input1, input2 : INTEGER RANGE 0 TO 100;
signal diff : INTEGER RANGE -100 TO 100;
signal result : STD_LOGIC_VECTOR(7 DOWNTO 0);

begin
process(input1, input2)
begin
    diff <= input1 - input2;

    if diff > 10 then
        result <= "10000000";
    elsif diff <= 10 and diff >= -10 then
        result <= "01000000";
    else
        result <= "00100000";
    end if;
end process;
-- 省略 --

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SignalSubtractor is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           Result : out  STD_LOGIC_VECTOR(7 downto 0));
end SignalSubtractor;

architecture Behavioral of SignalSubtractor is
begin
    -- AからBを減算して、結果を出力する
    Result <= A - B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DiffFilter is
    Port ( clk : in  STD_LOGIC;
           signal_in : in  STD_LOGIC_VECTOR(7 downto 0);
           signal_out : out STD_LOGIC_VECTOR(7 downto 0));
end DiffFilter;

architecture Behavioral of DiffFilter is
    signal prev_signal : STD_LOGIC_VECTOR(7 downto 0) := "00000000"; -- 前回の信号値を保存
begin
    process(clk)
    begin
        if rising_edge(clk) then
            signal_out <= signal_in - prev_signal; -- 現在の信号から前回の信号を減算
            prev_signal <= signal_in; -- 現在の信号を保存
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DiffTrigger is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           Threshold : in STD_LOGIC_VECTOR(7 downto 0);
           Trigger : out STD_LOGIC);
end DiffTrigger;

architecture Behavior of DiffTrigger is
begin
    process(A, B, Threshold)
    begin
        -- 入力値AとBの差分を計算
        if A - B > Threshold or B - A > Threshold then
            Trigger <= '1';  -- しきい値を超えた場合にトリガー
        else
            Trigger <= '0';
        end if;
    end process;
end Behavior;

-- 以下の部分をDiffTriggerエンティティに追加
Port ( SetThreshold : in STD_LOGIC_VECTOR(7 downto 0));
...
process(A, B, SetThreshold)
begin
    Threshold <= SetThreshold;  -- しきい値を動的に設定
    ...
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity subtraction is
port (
    A, B : in STD_LOGIC_VECTOR(1 downto 0);
    Result : out STD_LOGIC_VECTOR(1 downto 0);
    ErrorMsg : out STD_LOGIC_VECTOR(6 downto 0)
);
end entity;

architecture Behavioral of subtraction is
begin
    process(A, B)
    begin
        if (A - B) < "00" then
            ErrorMsg <= "エラー";
        else
            Result <= A - B;
        end if;
    end process;
end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity subtract_different_bits is
port (
    A : in STD_LOGIC_VECTOR(7 downto 0);
    B : in STD_LOGIC_VECTOR(3 downto 0);
    Result : out STD_LOGIC_VECTOR(7 downto 0)
);
end entity;

architecture Behavioral of subtract_different_bits is
begin
    process(A, B)
    begin
        Result <= A - ("0000" & B);
    end process;
end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity custom_sub is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           Y : out STD_LOGIC_VECTOR(7 downto 0));
end custom_sub;

architecture Behavioral of custom_sub is
function subtract_custom(a: STD_LOGIC_VECTOR; b: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
    variable temp : STD_LOGIC_VECTOR(7 downto 0);
begin
    -- ここでaからbを減算して、カスタマイズした処理を行う
    temp := a - b - "00000001"; -- 1をさらに引く
    return temp;
end function subtract_custom;

begin
    Y <= subtract_custom(A, B);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clip_sub is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           Y : out STD_LOGIC_VECTOR(7 downto 0));
end clip_sub;

architecture Behavioral of clip_sub is
begin
process(A, B)
    variable temp : STD_LOGIC_VECTOR(7 downto 0);
begin
    temp := A - B;
    if temp < "00000000" then
        Y <= "00000000"; -- 結果が0未満の場合は0にクリッピング
    elsif temp > "11111111" then
        Y <= "11111111"; -- 結果が255を超える場合は255にクリッピング
    else
        Y <= temp;
    end if;
end process;
end Behavioral;