VHDL順序回路の使い方10選！初心者でも簡単にマスター

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample_sequential is
    Port ( clk : in STD_LOGIC;
           d : in STD_LOGIC;
           q : out STD_LOGIC);
end sample_sequential;

architecture Behavioral of sample_sequential is
    signal tmp_q: STD_LOGIC;
begin
    process(clk)
    begin
        if rising_edge(clk) then -- クロックの立ち上がりエッジを検出
            tmp_q <= d; -- データをtmp_qに保存
        end if;
    end process;

    q <= tmp_q; -- フリップフロップの出力
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity simple_seq is
    Port ( clk : in STD_LOGIC;
           d : in STD_LOGIC;
           q : out STD_LOGIC);
end simple_seq;

architecture Behavioral of simple_seq is
signal r : STD_LOGIC;
begin
    process(clk)
    begin
        -- クロックの立ち上がりエッジで動作
        if rising_edge(clk) then
            r <= d;  -- 入力dをレジスタrに格納
        end if;
    end process;
    q <= r;  -- レジスタの値を出力
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity conditional_seq is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           d : in STD_LOGIC;
           q : out STD_LOGIC);
end conditional_seq;

architecture Behavioral of conditional_seq is
signal r : STD_LOGIC;
begin
    process(clk, rst)
    begin
        if rst = '1' then  -- リセットがアクティブなら
            r <= '0';      -- レジスタを0にリセット
        elsif rising_edge(clk) then
            r <= d;
        end if;
    end process;
    q <= r;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity loop_seq is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           q : out STD_LOGIC_VECTOR(3 downto 0));
end loop_seq;

architecture Behavioral of loop_seq is
signal count : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    process(clk, rst)
    begin
        if rst = '1' then
            count <= "0000";
        elsif rising_edge(clk) then
            count <= count + 1;
        end if;
    end process;
    q <= count;
end Behavioral;

entity counter is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(7 downto 0));
end counter;

architecture Behavioral of counter is
    signal cnt : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
    process(clk, rst)
    begin
        -- クロックの立ち上がりエッジで動作
        if rising_edge(clk) then
            if rst = '1' then
                cnt <= "00000000"; -- リセット時
            else
                if cnt = "11111111" then
                    cnt <= "00000000"; -- カウント値が最大になった場合
                else
                    cnt <= cnt + 1; -- カウントアップ
                end if;
            end if;
        end if;
    end process;

    count <= cnt; -- 出力
end Behavioral;

entity multi_signal is
    Port ( clk : in STD_LOGIC;
           A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : out STD_LOGIC);
end multi_signal;

architecture Behavioral of multi_signal is
begin
    process(clk)
    begin
        -- クロックの立ち上がりエッジで動作
        if rising_edge(clk) then
            if A = '1' and B = '0' then
                C <= '1';
            else
                C <= '0';
            end if;
        end if;
    end process;
end Behavioral;

entity external_input is
    Port ( clk : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(3 downto 0);
           LED : out STD_LOGIC_VECTOR(3 downto 0));
end external_input;

architecture Behavioral of external_input is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            LED <= data_in;
        end if;
    end process;
end Behavioral;

process(clock, reset)
begin
  if reset = '1' then
    -- counterの初期化がない
  elsif rising_edge(clock) then
    counter <= counter + 1;
  end if;
end process;

process(clock1)
begin
  if rising_edge(clock1) then
    output_signal <= '1';
  end if;
end process;

process(clock2)
begin
  if rising_edge(clock2) then
    output_signal <= '0';
  end if;
end process;

process(clock, reset)
begin
  if reset = '1' then
    counter <= (others => '0');
  elsif rising_edge(clock) then
    counter <= counter + 1;
  end if;
end process;

vhdl
signal mutex: std_logic := '0';

process(clock1)
begin
  if rising_edge(clock1) and mutex = '0' then
    output_signal <= '1';
    mutex <= '1';
  end if;
end process;

process(clock2)
begin
  if rising_edge(clock2) and mutex = '1' then
    output_signal <= '0';
    mutex <= '0';
  end if;
end process;

module counter_module (
    input clock,
    input reset,
    output reg [3:0] count
);

always @(posedge clock or posedge reset) begin
    if (reset) begin
        count <= 4'b0000;
    end else begin
        count <= count + 4'b0001;
    end
end

endmodule

module main_module (
    input a,
    input b,
    input select_signal,
    output y
);

// 外部モジュールのインスタンス化
multiplexer_module U1 (
    .input1(a),
    .input2(b),
    .select(select_signal),
    .output(y)
);

endmodule

module tb_counter();

reg clock;
reg reset;
wire [3:0] count_output;

// カウンタモジュールのインスタンス化
counter_module U1 (
    .clock(clock),
    .reset(reset),
    .count(count_output)
);

// クロック信号の生成
always begin
    #5 clock = ~clock;
end

// テストシーケンスの生成
initial begin
    reset = 1;
    #10 reset = 0;
    #50 reset = 1;
    #10 $finish;
end

endmodule