VHDLで絶対値を扱う10のコード例

ENTITY abs_basic IS
  PORT( 
    data_in  : IN  INTEGER;
    data_out : OUT INTEGER
  );
END ENTITY;

ARCHITECTURE behavior OF abs_basic IS
BEGIN
  PROCESS(data_in)
  BEGIN
    IF data_in < 0 THEN
      data_out <= -data_in;
    ELSE
      data_out <= data_in;
    END IF;
  END PROCESS;
END ARCHITECTURE;

entity abs_using_if is
    Port ( num : in  signed(7 downto 0);
           result : out signed(7 downto 0));
end abs_using_if;

architecture Behavioral of abs_using_if is
begin
process (num)
begin
    if num < 0 then
        result <= -num;
    else
        result <= num;
    end if;
end process;
end Behavioral;

entity abs_using_function is
    Port ( num : in  signed(7 downto 0);
           result : out signed(7 downto 0));
end abs_using_function;

architecture Behavioral of abs_using_function is
function get_absolute_value(input: signed) return signed is
begin
    if input < 0 then
        return -input;
    else
        return input;
    end if;
end function;

begin
    result <= get_absolute_value(num);
end Behavioral;

entity abs_using_bit is
    Port ( num : in  signed(7 downto 0);
           result : out signed(7 downto 0));
end abs_using_bit;

architecture Behavioral of abs_using_bit is
begin
process (num)
begin
    if num(7) = '1' then
        result <= -num;
    else
        result <= num;
    end if;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sort_abs is
    Port ( data_in : in  std_logic_vector(31 downto 0);
           data_out : out  std_logic_vector(31 downto 0));
end sort_abs;

architecture Behavioral of sort_abs is
begin
process(data_in)
    variable temp : std_logic_vector(31 downto 0);
begin
    temp := data_in;
    if temp(31) = '1' then -- 最上位ビットで符号判定
        temp := temp*(-1); -- 負の場合、値を反転
    end if;
    data_out <= temp; -- 絶対値を出力
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity signal_process is
    Port ( signal_in : in  std_logic_vector(15 downto 0);
           threshold : in  std_logic_vector(15 downto 0);
           signal_out : out  std_logic);
end signal_process;

architecture Behavioral of signal_process is
begin
process(signal_in, threshold)
    variable abs_signal : std_logic_vector(15 downto 0);
begin
    abs_signal := signal_in;
    if abs_signal(15) = '1' then -- 最上位ビットで符号判定
        abs_signal := abs_signal*(-1); -- 負の場合、値を反転
    end if;
    if abs_signal >= threshold then
        signal_out <= '1'; -- 閾値以上ならば出力
    else
        signal_out <= '0';
    end if;
end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DataConversion is
    Port ( int_input : in  STD_LOGIC_VECTOR(15 downto 0);
           float_output : out STD_LOGIC_VECTOR(31 downto 0));
end DataConversion;

architecture Behavioral of DataConversion is
    signal int_temp: integer;
    signal float_temp: real;
begin
    process(int_input)
    begin
        int_temp <= CONV_INTEGER(int_input); -- 整数型への変換
        if int_temp < 0 then
            int_temp <= -int_temp; -- 絶対値の取得
        end if;
        float_temp <= TO_FLOAT(int_temp); -- 浮動小数点型への変換
        float_output <= CONV_STD_LOGIC_VECTOR(float_temp, 32);
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AbsoluteValueModule is
    Port ( input : in  std_logic_vector(7 downto 0);
           output : out std_logic_vector(7 downto 0));
end AbsoluteValueModule;

architecture Behavioral of AbsoluteValueModule is
begin
    process(input)
    begin
        -- このコードでは、入力値の最上位ビットを確認して絶対値を出力します。
        if input(7) = '1' then -- 最上位ビットが1の場合、入力は負の数です
            output <= not input + "00000001"; -- 符号を反転して+1を追加して2の補数を取得
        else
            output <= input; -- 入力が正の数の場合、そのまま出力
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity abs_optimized is
    Port ( A : in  STD_LOGIC_VECTOR(31 downto 0);
           B : out STD_LOGIC_VECTOR(31 downto 0));
end abs_optimized;

architecture Behavior of abs_optimized is
begin
    process(A)
    begin
        if A(31) = '1' then
            B <= not(A) + "00000000000000000000000000000001";
        else
            B <= A;
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity abs_simulation is
    Port ( input_signal : in std_logic_vector(7 downto 0);
           threshold : in std_logic_vector(7 downto 0);
           result : out std_logic);
end abs_simulation;

architecture Behavior of abs_simulation is
begin
    process(input_signal, threshold)
    variable abs_val : std_logic_vector(7 downto 0);
    begin
        -- 絶対値の取得
        if input_signal(7) = '1' then -- MSBが1ならば、負の値
            abs_val := not input_signal + "00000001";
        else
            abs_val := input_signal;
        end if;

        -- 絶対値の比較
        if abs_val > threshold then
            result <= '1';
        else
            result <= '0';
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity abs_int is
    Port ( num : in  integer;
           abs_val : out  integer);
end abs_int;

architecture Behavioral of abs_int is
begin
    process(num)
    begin
        if num < 0 then
            abs_val <= -num;
        else
            abs_val <= num;
        end if;
    end process;
end Behavioral;

-- 必要なライブラリの追加
-- (中略)

entity abs_fixed is
    -- ポート定義
    -- (中略)
end abs_fixed;

architecture Behavioral of abs_fixed is
function abs_fixed_point(value: fixed_point_type) return fixed_point_type is
    begin
        if value < 0.0 then
            return -value;
        else
            return value;
        end if;
    end function;

    process(num)
    begin
        abs_val <= abs_fixed_point(num);
    end process;
end Behavioral;

-- 必要なライブラリの追加
-- (中略)

entity abs_overflow is
    -- ポート定義
    -- (中略)
end abs_overflow;

architecture Behavioral of abs_overflow is
    signal is_overflow: boolean := false;

    process(num)
    begin
        if num = INTEGER'LOW then
            is_overflow <= true;
            abs_val <= INTEGER'HIGH;
        else
            if num < 0 then
                abs_val <= -num;
            else
                abs_val <= num;
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity abs_custom is
    Port ( input : in  signed(7 downto 0);
           output : out  signed(7 downto 0));
end abs_custom;

architecture Behavioral of abs_custom is
begin
    process(input)
    begin
        -- 特定の条件下での処理を追加
        if input < "-50" then
            output <= "-50";
        else
            output <= abs(input);
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fast_abs is
    Port ( input : in  signed(7 downto 0);
           output : out  signed(7 downto 0));
end fast_abs;

architecture Behavioral of fast_abs is
begin
    process(input)
    variable temp: signed(7 downto 0);
    begin
        -- 最上位ビットで符号を判定
        if input(7) = '1' then  -- 負の場合
            temp := not input + "1";
        else
            temp := input;
        end if;
        output <= temp;
    end process;
end Behavioral;