VHDLでのビット幅可変の10の驚くべき方法

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample_entity is
end sample_entity;

architecture sample_arch of sample_entity is
    signal my_signal : std_logic_vector(7 downto 0);
begin
end sample_arch;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample1 is
end sample1;

architecture Behavioral of sample1 is
    signal bit8_signal : std_logic_vector(7 downto 0);
    signal bit16_signal : std_logic_vector(15 downto 0);
begin
    bit8_signal <= "01010101";
    bit16_signal <= "1100110011001100";
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample2 is
end sample2;

architecture Behavioral of sample2 is
    signal bit8_signal : std_logic_vector(7 downto 0) := "01010101";
    signal bit16_signal : std_logic_vector(15 downto 0);
begin
    bit16_signal <= "00000000" & bit8_signal;  -- 上位8ビットを0で埋めて拡張
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample3 is
end sample3;

architecture Behavioral of sample3 is
    signal bit16_signal : std_logic_vector(15 downto 0) := "1100110011001100";
    signal bit8_signal : std_logic_vector(7 downto 0);
begin
    bit8_signal <= bit16_signal(15 downto 8);  -- 上位8ビットを取り出す
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder is
    Generic ( WIDTH : integer := 8 ); -- ビット幅のデフォルトを8に設定
    Port ( A : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
           B : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
           SUM : out STD_LOGIC_VECTOR(WIDTH-1 downto 0) );
end adder;

architecture Behavioral of adder is
begin
    SUM <= A + B;  -- 加算操作
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity avg_calculator is
    Generic ( WIDTH : integer := 8 );
    Port ( A : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
           B : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
           AVG : out STD_LOGIC_VECTOR(WIDTH-1 downto 0) );
end avg_calculator;

architecture Behavioral of avg_calculator is
begin
    AVG <= (A + B) / 2;  -- 平均を計算
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity register_module is
    Generic ( WIDTH : integer := 8 );
    Port ( INPUT : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
           CLK : in STD_LOGIC;
           OUTPUT : out STD_LOGIC_VECTOR(WIDTH-1 downto 0) );
end register_module;

architecture Behavioral of register_module is
    signal temp : STD_LOGIC_VECTOR(WIDTH-1 downto 0);
begin
    process(CLK)
    begin
        if rising_edge(CLK) then
            temp <= INPUT;
        end if;
    end process;

    OUTPUT <= temp;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adaptive_module is
    Port ( DATA_IN : in STD_LOGIC_VECTOR(15 downto 0);
           WIDTH_IN : in INTEGER range 1 to 16;
           DATA_OUT : out STD_LOGIC_VECTOR(15 downto 0) );
end adaptive_module;

architecture Behavioral of adaptive_module is
begin
    DATA_OUT <= DATA_IN(WIDTH_IN-1 downto 0) & (16-WIDTH_IN) others => '0';
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity adder is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           SUM : out STD_LOGIC_VECTOR(8 downto 0) );
end adder;

architecture Behavioral of adder is
begin
    SUM <= std_logic_vector(unsigned(A) + unsigned(B));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bit_doubler is
    Port ( INPUT : in  STD_LOGIC_VECTOR(15 downto 0);
           OUTPUT : out STD_LOGIC_VECTOR(31 downto 0) );
end bit_doubler;

architecture Behavioral of bit_doubler is
begin
    OUTPUT <= INPUT & INPUT;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CustomBitWidth is
    Port ( clk : in STD_LOGIC;
           inputData : in STD_LOGIC_VECTOR(15 downto 0);
           outputData : out STD_LOGIC_VECTOR(15 downto 0));
end CustomBitWidth;

architecture Behavior of CustomBitWidth is
    signal tempData : STD_LOGIC_VECTOR(15 downto 0);
begin
    process(clk)
    begin
        -- 条件に応じてビット幅を調整
        if inputData(15) = '1' then
            tempData <= "0000" & inputData(11 downto 0);
        else
            tempData <= inputData;
        end if;
    end process;
    outputData <= tempData;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DynamicBitWidthChange is
    Port ( clk : in STD_LOGIC;
           inputData : in STD_LOGIC_VECTOR(31 downto 0);
           outputData : out STD_LOGIC_VECTOR(31 downto 0));
end DynamicBitWidthChange;

architecture Behavior of DynamicBitWidthChange is
    signal avg : STD_LOGIC_VECTOR(31 downto 0);
begin
    process(clk)
    begin
        -- 入力データの平均値を計算
        avg <= inputData / "00000010"; 
        if avg < "00001000" then
            outputData <= "00000000" & avg(7 downto 0);
        else
            outputData <= avg;
        end if;
    end process;
end Behavior;

-- ここでは、簡単のために浮動小数点から整数への変換のみを示します。
library

 IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FloatToIntConversion is
    Port ( clk : in STD_LOGIC;
           floatInput : in STD_LOGIC_VECTOR(15 downto 0);
           intOutput : out STD_LOGIC_VECTOR(31 downto 0));
end FloatToIntConversion;

architecture Behavior of FloatToIntConversion is
    signal temp : INTEGER;
begin
    process(clk)
    begin
        -- 簡単のために、浮動小数点の変換は省略
        temp <= TO_INTEGER(TO_UNSIGNED(floatInput, 16));
        intOutput <= STD_LOGIC_VECTOR(TO_UNSIGNED(temp, 32));
    end process;
end Behavior;