VHDLで理解する比較演算子の基本と活用15選

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity comparator is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           equal : out STD_LOGIC;
           greater : out STD_LOGIC;
           less : out STD_LOGIC);
end comparator;

architecture Behavioral of comparator is
begin
    process(A, B)
    begin
        equal <= '0';
        greater <= '0';
        less <= '0';

        if unsigned(A) = unsigned(B) then
            equal <= '1';
        elsif unsigned(A) > unsigned(B) then
            greater <= '1';
        else
            less <= '1';
        end if;
    end process;
end Behavioral;

if A = B then
    -- Aが　B と等しい場合の処理
elsif A > B then
    -- Aが　B より大きい場合の処理
else
    -- それ以外の場合の処理
end if;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity complex_comparator is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           C : in  STD_LOGIC_VECTOR (7 downto 0);
           result : out STD_LOGIC);
end complex_comparator;

architecture Behavioral of complex_comparator is
begin
    process(A, B, C)
    begin
        result <= '0';

        if (unsigned(A) > unsigned(B)) and (unsigned(B) >= unsigned(C)) then
            result <= '1';
        elsif (unsigned(A) = unsigned(B)) and (unsigned(B) < unsigned(C)) then
            result <= '1';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bit_pattern_detector is
    Port ( data : in  STD_LOGIC_VECTOR (7 downto 0);
           pattern_detected : out STD_LOGIC);
end bit_pattern_detector;

architecture Behavioral of bit_pattern_detector is
begin
    process(data)
    begin
        -- ビットパターン "101" を検出
        pattern_detected <= '0';
        if ((data(7 downto 5) = "101") or
            (data(6 downto 4) = "101") or
            (data(5 downto 3) = "101") or
            (data(4 downto 2) = "101") or
            (data(3 downto 1) = "101") or
            (data(2 downto 0) = "101")) then
            pattern_detected <= '1';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity masked_comparator is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           mask : in  STD_LOGIC_VECTOR (7 downto 0);
           match : out STD_LOGIC);
end masked_comparator;

architecture Behavioral of masked_comparator is
begin
    process(A, B, mask)
        variable masked_A, masked_B : STD_LOGIC_VECTOR (7 downto 0);
    begin
        masked_A := A and mask;
        masked_B := B and mask;

        if masked_A = masked_B then
            match <= '1';
        else
            match <= '0';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity bit_diff_detector is
    Port ( A : in  STD_LOGIC_VECTOR (7 downto 0);
           B : in  STD_LOGIC_VECTOR (7 downto 0);
           diff : out STD_LOGIC_VECTOR (7 downto 0));
end bit_diff_detector;

architecture Behavioral of bit_diff_detector is
begin
    process(A, B)
        variable xor_result : STD_LOGIC_VECTOR (7 downto 0);
    begin
        xor_result := A xor B;

        for i in 0 to 7 loop
            if xor_result(i) = '1' then
                diff(i) <= '1';  -- 差分あり
            else
                diff(i) <= '0';  -- 差分なし
            end if;
        end loop;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity power_of_two_detector is
    Port ( input : in  STD_LOGIC_VECTOR (7 downto 0);
           is_power_of_two : out STD_LOGIC);
end power_of_two_detector;

architecture Behavioral of power_of_two_detector is
begin
    process(input)
        variable input_unsigned : unsigned(7 downto 0);
        variable shifted : unsigned(7 downto 0);
    begin
        input_unsigned := unsigned(input);
        shifted := input_unsigned - 1;

        if input_unsigned /= 0 and (input_unsigned and shifted) = 0 then
            is_power_of_two <= '1';
        else
            is_power_of_two <= '0';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity max_consecutive_ones is
    Port ( input : in  STD_LOGIC_VECTOR (7 downto 0);
           max_ones : out STD_LOGIC_VECTOR (3 downto 0));
end max_consecutive_ones;

architecture Behavioral of max_consecutive_ones is
begin
    process(input)
        variable count : unsigned(3 downto 0) := (others => '0');
        variable max_count : unsigned(3 downto 0) := (others => '0');
        variable temp : unsigned(7 downto 0);
    begin
        temp := unsigned(input);
        count := (others => '0');
        max_count := (others => '0');

        for i in 0 to 7 loop
            if temp(0) = '1' then
                count := count + 1;
                if count > max_count then
                    max_count := count;
                end if;
            else
                count := (others => '0');
            end if;
            temp := shift_right(temp, 1);
        end loop;

        max_ones <= std_logic_vector(max_count);
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity palindrome_checker is
    Port ( input : in  STD_LOGIC_VECTOR (7 downto 0);
           is_palindrome : out STD_LOGIC);
end palindrome_checker;

architecture Behavioral of palindrome_checker is
begin
    process(input)
        variable reversed : STD_LOGIC_VECTOR (7 downto 0);
        variable temp : STD_LOGIC_VECTOR (7 downto 0);
    begin
        temp := input;
        for i in 0 to 7 loop
            reversed(i) := temp(7);
            temp := temp(6 downto 0) & '0';  -- Left shift
        end loop;

        if input = reversed then
            is_palindrome <= '1';
        else
            is_palindrome <= '0';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity two_bit_comparator is
    Port ( A : in  STD_LOGIC_VECTOR (1 downto 0);
           B : in  STD_LOGIC_VECTOR (1 downto 0);
           A_greater : out STD_LOGIC;
           A_equal : out STD_LOGIC;
           A_less : out STD_LOGIC);
end two_bit_comparator;

architecture Behavioral of two_bit_comparator is
begin
    process(A, B)
    begin
        if unsigned(A) > unsigned(B) then
            A_greater <= '1';
            A_equal <= '0';
            A_less <= '0';
        elsif unsigned(A) = unsigned(B) then
            A_greater <= '0';
            A_equal <= '1';
            A_less <= '0';
        else
            A_greater <= '0';
            A_equal <= '0';
            A_less <= '1';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity four_bit_magnitude_comparator is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           A_greater : out STD_LOGIC;
           A_equal : out STD_LOGIC;
           A_less : out STD_LOGIC);
end four_bit_magnitude_comparator;

architecture Behavioral of four_bit_magnitude_comparator is
begin
    process(A, B)
        variable A_uint, B_uint : unsigned(3 downto 0);
    begin
        A_uint := unsigned(A);
        B_uint := unsigned(B);

        if A_uint > B_uint then
            A_greater <= '1';
            A_equal <= '0';
            A_less <= '0';
        elsif A_uint = B_uint then
            A_greater <= '0';
            A_equal <= '1';
            A_less <= '0';
        else
            A_greater <= '0';
            A_equal <= '0';
            A_less <= '1';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity priority_encoder_8bit is
    Port ( input : in  STD_LOGIC_VECTOR (7 downto 0);
           output : out STD_LOGIC_VECTOR (2 downto 0);
           valid : out STD_LOGIC);
end priority_encoder_8bit;

architecture Behavioral of priority_encoder_8bit is
begin
    process(input)
    begin
        valid <= '0';
        output <= "000";

        if input(7) = '1' then
            output <= "111";
            valid <= '1';
        elsif input(6) = '1' then
            output <= "110";
            valid <= '1';
        elsif input(5) = '1' then
            output <= "101";
            valid <= '1';
        elsif input(4) = '1' then
            output <= "100";
            valid <= '1';
        elsif input(3) = '1' then
            output <= "011";
            valid <= '1';
        elsif input(2) = '1' then
            output <= "010";
            valid <= '1';
        elsif input(1) = '1' then
            output <= "001";
            valid <= '1';
        elsif input(0) = '1' then
            output <= "000";
            valid <= '1';
        end if;
    end process;
end Behavioral;

signal A : STD_LOGIC_VECTOR(3 downto 0);
signal B : integer range 0 to 15;

-- エラー：型の不一致
if A > B then
    -- 処理
end if;

signal A : STD_LOGIC_VECTOR(3 downto 0);
signal B : integer range 0 to 15;

-- 正しい比較
if to_integer(unsigned(A)) > B then
    -- 処理
end if;

signal result : STD_LOGIC;

-- エラー：代入ではなく比較を行おうとしている
if A = B then
    result := '1';  -- 誤：代入演算子を使用
else
    result := '0';  -- 誤：代入演算子を使用
end if;

signal result : STD_LOGIC;

-- 正しい使用法
if A = B then
    result <= '1';  -- 正：信号への代入には '<=' を使用
else
    result <= '0';  -- 正：信号への代入には '<=' を使用
end if;

-- タイミング違反の可能性がある複雑な比較
if (A > B and C > D and E > F and G > H) then
    result <= '1';
else
    result <= '0';
end if;

signal stage1, stage2 : STD_LOGIC;

process(clk)
begin
    if rising_edge(clk) then
        -- Stage 1
        if (A > B and C > D) then
            stage1 <= '1';
        else
            stage1 <= '0';
        end if;

        -- Stage 2
        if (E > F and G > H) then
            stage2 <= '1';
        else
            stage2 <= '0';
        end if;

        -- Final result
        result <= stage1 and stage2;
    end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.FLOAT_PKG.ALL;

entity float_comparator is
    Port ( A : in  float32;
           B : in  float32;
           epsilon : in  float32;
           is_equal : out STD_LOGIC;
           is_greater : out STD_LOGIC;
           is_less : out STD_LOGIC);
end float_comparator;

architecture Behavioral of float_comparator is
begin
    process(A, B, epsilon)
        variable diff : float32;
    begin
        diff := abs(A - B);

        if diff <= epsilon then
            is_equal <= '1';
            is_greater <= '0';
            is_less <= '0';
        elsif A > B then
            is_equal <= '0';
            is_greater <= '1';
            is_less <= '0';
        else
            is_equal <= '0';
            is_greater <= '0';
            is_less <= '1';
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity string_comparator is
    Port ( str1 : in  STD_LOGIC_VECTOR (31 downto 0);
           str2 : in  STD_LOGIC_VECTOR (31 downto 0);
           str_equal : out STD_LOGIC);
end string_comparator;

architecture Behavioral of string_comparator is
begin
    process(str1, str2)
        variable equal : STD_LOGIC := '1';
    begin
        for i in 0 to 3 loop
            if str1(8*i+7 downto 8*i) /= str2(8*i+7 downto 8*i) then
                equal := '0';
                exit;
            end if;
        end loop;

        str_equal <= equal;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity matrix_max_finder is
    Port ( matrix : in  array (0 to 1, 0 to 1) of unsigned(7 downto 0);
           max_value : out unsigned(7 downto 0);
           max_row : out unsigned(0 downto 0);
           max_col : out unsigned(0 downto 0));
end matrix_max_finder;

architecture Behavioral of matrix_max_finder is
begin
    process(matrix)
        variable current_max : unsigned(7 downto 0) := (others => '0');
        variable max_r, max_c : unsigned(0 downto 0) := (others => '0');
    begin
        for i in 0 to 1 loop
            for j in 0 to 1 loop
                if matrix(i, j) > current_max then
                    current_max := matrix(i, j);
                    max_r := to_unsigned(i, 1);
                    max_c := to_unsigned(j, 1);
                end if;
            end loop;
        end loop;

        max_value <= current_max;
        max_row <= max_r;
        max_col <= max_c;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity optimized_state_machine is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           input : in  STD_LOGIC_VECTOR(7 downto 0);
           output : out STD_LOGIC_VECTOR(7 downto 0));
end optimized_state_machine;

architecture Behavioral of optimized_state_machine is
    type state_type is (IDLE, PROCESS_LOW, PROCESS_MID, PROCESS_HIGH);
    signal current_state, next_state : state_type;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= IDLE;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process(current_state, input)
    begin
        case current_state is
            when IDLE =>
                if unsigned(input) < 64 then
                    next_state <= PROCESS_LOW;
                elsif unsigned(input) < 192 then
                    next_state <= PROCESS_MID;
                else
                    next_state <= PROCESS_HIGH;
                end if;
                output <= (others => '0');

            when PROCESS_LOW =>
                next_state <= IDLE;
                output <= input;

            when PROCESS_MID =>
                next_state <= IDLE;
                output <= std_logic_vector(unsigned(input) + 1);

            when PROCESS_HIGH =>
                next_state <= IDLE;
                output <= std_logic_vector(unsigned(input) + 2);
        end case;
    end process;
end Behavioral;