VHDLにおける信号遅延の基本と実装15選

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity delay_example is
    Port ( clk : in STD_LOGIC;
           input : in STD_LOGIC;
           output : out STD_LOGIC);
end delay_example;

architecture Behavioral of delay_example is
    signal delayed_signal : STD_LOGIC;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            delayed_signal <= input;
            output <= delayed_signal;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity delay_assign_example is
    Port ( input : in STD_LOGIC;
           output : out STD_LOGIC);
end delay_assign_example;

architecture Behavioral of delay_assign_example is
begin
    output <= transport input after 10 ns;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity delay_process_example is
    Port ( clk : in STD_LOGIC;
           input : in STD_LOGIC;
           output : out STD_LOGIC);
end delay_process_example;

architecture Behavioral of delay_process_example is
    signal delay_buffer : STD_LOGIC_VECTOR(2 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            delay_buffer <= delay_buffer(1 downto 0) & input;
            output <= delay_buffer(2);
        end if;
    end process;
end Behavioral;

constant DELAY_TIME : time := 5 ns;
signal_out <= signal_in after DELAY_TIME;

process(clk)
begin
    if rising_edge(clk) then
        A <= B after 5 ns;
        B <= A after 5 ns;
    end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity delay_tb is
end delay_tb;

architecture Behavioral of delay_tb is
    signal clk : std_logic := '0';
    signal input, output : std_logic;

    -- テスト対象のコンポーネント
    component delay_component is
        Port ( clk : in STD_LOGIC;
               input : in STD_LOGIC;
               output : out STD_LOGIC);
    end component;

begin
    -- テスト対象のインスタンス化
    uut: delay_component port map (clk => clk, input => input, output => output);

    -- クロック生成プロセス
    clk_process: process
    begin
        wait for 5 ns;
        clk <= not clk;
    end process;

    -- テストシーケンス
    stim_proc: process
    begin
        input <= '0';
        wait for 100 ns;
        input <= '1';
        wait for 100 ns;
        input <= '0';
        wait for 100 ns;
        wait;
    end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity async_sync_delay is
    Port ( clk : in STD_LOGIC;
           async_in : in STD_LOGIC;
           sync_in : in STD_LOGIC;
           async_out : out STD_LOGIC;
           sync_out : out STD_LOGIC);
end async_sync_delay;

architecture Behavioral of async_sync_delay is
    signal sync_reg : STD_LOGIC_VECTOR(1 downto 0);
begin
    -- 非同期信号の遅延
    async_out <= async_in after 5 ns;

    -- 同期信号の遅延
    process(clk)
    begin
        if rising_edge(clk) then
            sync_reg <= sync_reg(0) & sync_in;
            sync_out <= sync_reg(1);
        end if;
    end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity standard_delay_example is
    Port ( input : in STD_LOGIC;
           output1 : out STD_LOGIC;
           output2 : out STD_LOGIC);
end standard_delay_example;

architecture Behavioral of standard_delay_example is
    constant DELAY1 : time := 10 ns;
    constant DELAY2 : time := 20 ns;
begin
    output1 <= input after DELAY1;
    output2 <= input after DELAY2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.VITAL_Timing.ALL;

entity ieee_delay_example is
    Port ( clk : in STD_LOGIC;
           data : in STD_LOGIC;
           output : out STD_LOGIC);
end ieee_delay_example;

architecture Behavioral of ieee_delay_example is
    constant Tviol_data_clk : VitalDelayType := 2 ns;
    constant Tsetup_data_clk : VitalDelayType := 1 ns;
    constant Thold_data_clk : VitalDelayType := 0.5 ns;

    signal Violation : X01 := '0';
begin
    VITALBehavior : process(clk, data)
        variable Tviol_data_clk_v : X01 := '0';
    begin
        VitalSetupHoldCheck (
            TestSignal => data,
            TestClock => clk,
            SetupHigh => Tsetup_data_clk,
            SetupLow => Tsetup_data_clk,
            HoldHigh => Thold_data_clk,
            HoldLow => Thold_data_clk,
            CheckEnabled => true,
            RefTransition => '/',
            TimingData => Tviol_data_clk_v,
            XOn => true,
            MsgOn => true,
            HeaderMsg => "/ieee_delay_example",
            TimingCheck => true
        );

        Violation <= Tviol_data_clk_v;

        if rising_edge(clk) and Violation = '0' then
            output <= data;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package temperature_delay_pkg is
    type temperature_range is range -40 to 125;
    function calculate_delay(temp : temperature_range) return time;
end package;

package body temperature_delay_pkg is
    function calculate_delay(temp : temperature_range) return time is
    begin
        -- 温度が上がるほど遅延が増加する簡単なモデル
        return (1 ns + (temp + 40) * 10 ps);
    end function;
end package body;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.temperature_delay_pkg.ALL;

entity custom_delay_example is
    Port ( input : in STD_LOGIC;
           temp : in temperature_range;
           output : out STD_LOGIC);
end custom_delay_example;

architecture Behavioral of custom_delay_example is
begin
    process(input, temp)
        variable delay : time;
    begin
        delay := calculate_delay(temp);
        output <= input after delay;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff_with_delay is
    Port ( clk : in STD_LOGIC;
           d : in STD_LOGIC;
           q : out STD_LOGIC);
end dff_with_delay;

architecture Behavioral of dff_with_delay is
    signal d_delayed : STD_LOGIC;
begin
    -- 入力信号に遅延を追加
    d_delayed <= d after 1 ns;

    process(clk)
    begin
        if rising_edge(clk) then
            q <= d_delayed;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ripple_counter_with_delay is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0));
end ripple_counter_with_delay;

architecture Behavioral of ripple_counter_with_delay is
    signal q : STD_LOGIC_VECTOR(3 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            q <= (others => '0');
        elsif rising_edge(clk) then
            q(0) <= not q(0);
        end if;
    end process;

    process(q(0))
    begin
        if falling_edge(q(0)) then
            q(1) <= not q(1) after 1 ns;
        end if;
    end process;

    process(q(1))
    begin
        if falling_edge(q(1)) then
            q(2) <= not q(2) after 2 ns;
        end if;
    end process;

    process(q(2))
    begin
        if falling_edge(q(2)) then
            q(3) <= not q(3) after 3 ns;
        end if;
    end process;

    count <= q;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity output_timing_example is
    Port ( clk : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC_VECTOR(7 downto 0);
           valid : out STD_LOGIC);
end output_timing_example;

architecture Behavioral of output_timing_example is
    signal data_reg : STD_LOGIC_VECTOR(7 downto 0);
    signal valid_reg : STD_LOGIC;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            data_reg <= data_in;
            valid_reg <= '1';
        end if;
    end process;

    -- 出力信号のタイミング調整
    data_out <= data_reg after 2 ns;
    valid <= valid_reg after 2 ns;
end Behavioral;

-- シミュレーション結果の一部
-- 時刻     信号名    値
-- 0 ns     clk       0
-- 5 ns     clk       1
-- 6 ns     data_in   10110101
-- 7 ns     valid     1
-- 8 ns     data_out  10110101

process(clk)
begin
    if rising_edge(clk) then
        data_out <= data_in;  -- 遅延が不足している可能性がある
    end if;
end process;

signal data_buffered : std_logic;

process(clk)
begin
    if rising_edge(clk) then
        data_buffered <= data_in;
        data_out <= data_buffered;
    end if;
end process;

process(clk)
begin
    if rising_edge(clk) then
        temp1 <= input1 and input2;
        temp2 <= temp1 or input3;
        temp3 <= temp2 xor input4;
        output <= temp3 and input5;
    end if;
end process;

process(clk)
begin
    if rising_edge(clk) then
        temp1 <= input1 and input2;
        temp2 <= temp1 or input3;
        temp3 <= temp2 xor input4;
    end if;
end process;

process(clk)
begin
    if rising_edge(clk) then
        output <= temp3 and input5;
    end if;
end process;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity high_speed_datapath is
    Port ( clk : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC);
end high_speed_datapath;

architecture Behavioral of high_speed_datapath is
    signal shift_reg : STD_LOGIC_VECTOR(7 downto 0);
    signal bit_counter : unsigned(2 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            -- データの並列入力
            if bit_counter = "000" then
                shift_reg <= data_in;
            else
                -- シフト処理
                shift_reg <= shift_reg(6 downto 0) & '0';
            end if;

            -- カウンタの更新
            bit_counter <= bit_counter + 1;

            -- 出力の生成（最上位ビットを出力）
            data_out <= shift_reg(7) after 1 ns;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clock_domain_crossing is
    Port ( clk_write : in STD_LOGIC;
           clk_read : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC_VECTOR(7 downto 0);
           write_en : in STD_LOGIC;
           read_en : in STD_LOGIC);
end clock_domain_crossing;

architecture Behavioral of clock_domain_crossing is
    type fifo_array is array (0 to 3) of STD_LOGIC_VECTOR(7 downto 0);
    signal fifo : fifo_array;
    signal write_ptr, read_ptr : integer range 0 to 3;
    signal write_ptr_gray, read_ptr_gray : STD_LOGIC_VECTOR(1 downto 0);
    signal write_ptr_sync, read_ptr_sync : STD_LOGIC_VECTOR(1 downto 0);
begin
    -- 書き込みプロセス
    write_process: process(clk_write)
    begin
        if rising_edge(clk_write) then
            if write_en = '1' then
                fifo(write_ptr) <= data_in;
                write_ptr <= (write_ptr + 1) mod 4;
            end if;
            -- グレイコードへの変換
            write_ptr_gray <= std_logic_vector(to_unsigned(write_ptr, 2) xor ('0' & to_unsigned(write_ptr, 2)(1)));
        end if;
    end process;

    -- 読み出しプロセス
    read_process: process(clk_read)
    begin
        if rising_edge(clk_read) then
            if read_en = '1' then
                data_out <= fifo(read_ptr) after 2 ns;
                read_ptr <= (read_ptr + 1) mod 4;
            end if;
            -- グレイコードへの変換
            read_ptr_gray <= std_logic_vector(to_unsigned(read_ptr, 2) xor ('0' & to_unsigned(read_ptr, 2)(1)));
        end if;
    end process;

    -- ポインタの同期化
    sync_write_ptr: process(clk_read)
    begin
        if rising_edge(clk_read) then
            write_ptr_sync <= write_ptr_gray after 1 ns;
        end if;
    end process;

    sync_read_ptr: process(clk_write)
    begin
        if rising_edge(clk_write) then
            read_ptr_sync <= read_ptr_gray after 1 ns;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity pipeline_multiplier is
    Port ( clk : in STD_LOGIC;
           a : in STD_LOGIC_VECTOR(7 downto 0);
           b : in STD_LOGIC_VECTOR(7 downto 0);
           result : out STD_LOGIC_VECTOR(15 downto 0));
end pipeline_multiplier;

architecture Behavioral of pipeline_multiplier is
    signal a_reg, b_reg : STD_LOGIC_VECTOR(7 downto 0);
    signal prod1, prod2, prod3 : unsigned(15 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            -- Stage 1: 入力レジスタ
            a_reg <= a after 0.5 ns;
            b_reg <= b after 0.5 ns;

            -- Stage 2: 乗算の開始
            prod1 <= unsigned(a_reg) * unsigned(b_reg(3 downto 0)) after 1 ns;

            -- Stage 3: 乗算の続き
            prod2 <= prod1 + (unsigned(a_reg) * unsigned(b_reg(7 downto 4)) & "0000") after 1 ns;

            -- Stage 4: 最終結果
            prod3 <= prod2 after 0.5 ns;
        end if;
    end process;

    result <= std_logic_vector(prod3);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity protocol_controller is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           start : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           tx : out STD_LOGIC;
           busy : out STD_LOGIC);
end protocol_controller;

architecture Behavioral of protocol_controller is
    type state_type is (IDLE, START_BIT, DATA_BITS, STOP_BIT);
    signal state, next_state : state_type;
    signal bit_counter : integer range 0 to 7;
    signal shift_reg : STD_LOGIC_VECTOR(7 downto 0);
begin
    -- 状態レジスタ
    process(clk, reset)
    begin
        if reset = '1' then
            state <= IDLE;
        elsif rising_edge(clk) then
            state <= next_state after 1 ns; -- 状態遷移に1nsの遅延を追加
        end if;
    end process;

    -- 次状態ロジックと出力ロジック
    process(state, start, bit_counter, shift_reg)
    begin
        next_state <= state;
        tx <= '1';
        busy <= '0';

        case state is
            when IDLE =>
                if start = '1' then
                    next_state <= START_BIT;
                    busy <= '1';
                end if;

            when START_BIT =>
                tx <= '0';
                busy <= '1';
                next_state <= DATA_BITS;

            when DATA_BITS =>
                tx <= shift_reg(0);
                busy <= '1';
                if bit_counter = 7 then
                    next_state <= STOP_BIT;
                end if;

            when STOP_BIT =>
                busy <= '1';
                next_state <= IDLE;
        end case;
    end process;

    -- ビットカウンタとシフトレジスタ
    process(clk, reset)
    begin
        if reset = '1' then
            bit_counter <= 0;
            shift_reg <= (others => '0');
        elsif rising_edge(clk) then
            case state is
                when IDLE =>
                    if start = '1' then
                        shift_reg <= data_in;
                    end if;
                when DATA_BITS =>
                    shift_reg <= '0' & shift_reg(7 downto 1);
                    bit_counter <= bit_counter + 1;
                when others =>
                    bit_counter <= 0;
            end case;
        end if;
    end process;
end Behavioral;