VHDLにおけるゲーティドクロックの設計手法と活用14選

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity BasicClockGating is
    Port ( clk : in STD_LOGIC;
           enable : in STD_LOGIC;
           gated_clk : out STD_LOGIC);
end BasicClockGating;

architecture Behavioral of BasicClockGating is
begin
    process(clk, enable)
    begin
        if rising_edge(clk) then
            gated_clk <= clk and enable;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ConditionalClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           data_valid : in STD_LOGIC;
           gated_clk : out STD_LOGIC);
end ConditionalClockGating;

architecture Behavioral of ConditionalClockGating is
    signal enable_latch : STD_LOGIC := '0';
begin
    process(clk, reset)
    begin
        if reset = '1' then
            enable_latch <= '0';
        elsif falling_edge(clk) then
            enable_latch <= data_valid;
        end if;
    end process;

    gated_clk <= clk and enable_latch;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity HierarchicalClockGating is
    Port ( main_clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable_module1 : in STD_LOGIC;
           enable_module2 : in STD_LOGIC;
           gated_clk1 : out STD_LOGIC;
           gated_clk2 : out STD_LOGIC);
end HierarchicalClockGating;

architecture Behavioral of HierarchicalClockGating is
    component BasicClockGating is
        Port ( clk : in STD_LOGIC;
               enable : in STD_LOGIC;
               gated_clk : out STD_LOGIC);
    end component;

    signal intermediate_clk : STD_LOGIC;
begin
    -- トップレベルのクロックゲーティング
    top_level_gating: BasicClockGating
    port map (
        clk => main_clk,
        enable => enable_module1 or enable_module2,
        gated_clk => intermediate_clk
    );

    -- モジュール1のクロックゲーティング
    module1_gating: BasicClockGating
    port map (
        clk => intermediate_clk,
        enable => enable_module1,
        gated_clk => gated_clk1
    );

    -- モジュール2のクロックゲーティング
    module2_gating: BasicClockGating
    port map (
        clk => intermediate_clk,
        enable => enable_module2,
        gated_clk => gated_clk2
    );
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity OptimizedClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           data : in STD_LOGIC_VECTOR(7 downto 0);
           gated_clk : out STD_LOGIC;
           processed_data : out STD_LOGIC_VECTOR(7 downto 0));
end OptimizedClockGating;

architecture Behavioral of OptimizedClockGating is
    signal enable_latch : STD_LOGIC := '0';
    signal internal_gated_clk : STD_LOGIC;
    signal data_reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    -- クロックゲーティングロジック
    process(clk, reset)
    begin
        if reset = '1' then
            enable_latch <= '0';
        elsif falling_edge(clk) then
            enable_latch <= enable;
        end if;
    end process;

    internal_gated_clk <= clk and enable_latch;
    gated_clk <= internal_gated_clk;

    -- データ処理ロジック
    process(internal_gated_clk, reset)
    begin
        if reset = '1' then
            data_reg <= (others => '0');
        elsif rising_edge(internal_gated_clk) then
            data_reg <= data + 1;  -- 簡単な処理の例
        end if;
    end process;

    processed_data <= data_reg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SRAM_with_ClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           write_enable : in STD_LOGIC;
           address : in STD_LOGIC_VECTOR(7 downto 0);
           data_in : in STD_LOGIC_VECTOR(31 downto 0);
           data_out : out STD_LOGIC_VECTOR(31 downto 0));
end SRAM_with_ClockGating;

architecture Behavioral of SRAM_with_ClockGating is
    type ram_type is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
    signal RAM : ram_type := (others => (others => '0'));
    signal gated_clk : STD_LOGIC;
    signal enable_latch : STD_LOGIC := '0';
begin
    -- クロックゲーティングロジック
    process(clk, reset)
    begin
        if reset = '1' then
            enable_latch <= '0';
        elsif falling_edge(clk) then
            enable_latch <= enable;
        end if;
    end process;

    gated_clk <= clk and enable_latch;

    -- SRAMロジック
    process(gated_clk)
    begin
        if rising_edge(gated_clk) then
            if write_enable = '1' then
                RAM(to_integer(unsigned(address))) <= data_in;
            end if;
            data_out <= RAM(to_integer(unsigned(address)));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SRAM_with_RetentionMode is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           retention_mode : in STD_LOGIC;
           write_enable : in STD_LOGIC;
           address : in STD_LOGIC_VECTOR(7 downto 0);
           data_in : in STD_LOGIC_VECTOR(31 downto 0);
           data_out : out STD_LOGIC_VECTOR(31 downto 0));
end SRAM_with_RetentionMode;

architecture Behavioral of SRAM_with_RetentionMode is
    type ram_type is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
    signal RAM : ram_type := (others => (others => '0'));
    signal gated_clk : STD_LOGIC;
    signal enable_latch : STD_LOGIC := '0';
    signal power_enable : STD_LOGIC;
begin
    -- クロックゲーティングロジック
    process(clk, reset)
    begin
        if reset = '1' then
            enable_latch <= '0';
        elsif falling_edge(clk) then
            enable_latch <= enable and not retention_mode;
        end if;
    end process;

    gated_clk <= clk and enable_latch;
    power_enable <= not retention_mode;

    -- SRAMロジック
    process(gated_clk, power_enable)
    begin
        if power_enable = '0' then
            -- 待機保持モード：データを保持するが、アクセスは不可
            null;
        elsif rising_edge(gated_clk) then
            if write_enable = '1' then
                RAM(to_integer(unsigned(address))) <= data_in;
            end if;
            data_out <= RAM(to_integer(unsigned(address)));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SRAM_with_ToggleRateControl is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           write_enable : in STD_LOGIC;
           address : in STD_LOGIC_VECTOR(7 downto 0);
           data_in : in STD_LOGIC_VECTOR(31 downto 0);
           data_out : out STD_LOGIC_VECTOR(31 downto 0));
end SRAM_with_ToggleRateControl;

architecture Behavioral of SRAM_with_ToggleRateControl is
    type ram_type is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
    signal RAM : ram_type := (others => (others => '0'));
    signal gated_clk : STD_LOGIC;
    signal enable_latch : STD_LOGIC := '0';
    signal toggle_counter : unsigned(3 downto 0) := (others => '0');
    signal toggle_threshold : unsigned(3 downto 0) := "1000"; -- 8回に1回クロックを有効化
begin
    -- クロックゲーティングロジック
    process(clk, reset)
    begin
        if reset = '1' then
            enable_latch <= '0';
            toggle_counter <= (others => '0');
        elsif falling_edge(clk) then
            if enable = '1' then
                if toggle_counter = toggle_threshold - 1 then
                    enable_latch <= '1';
                    toggle_counter <= (others => '0');
                else
                    enable_latch <= '0';
                    toggle_counter <= toggle_counter + 1;
                end if;
            else
                enable_latch <= '0';
                toggle_counter <= (others => '0');
            end if;
        end if;
    end process;

    gated_clk <= clk and enable_latch;

    -- SRAMロジック
    process(gated_clk)
    begin
        if rising_edge(gated_clk) then
            if write_enable = '1' then
                RAM(to_integer(unsigned(address))) <= data_in;
            end if;
            data_out <= RAM(to_integer(unsigned(address)));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SRAM_with_PowerGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           power_down : in STD_LOGIC;
           write_enable : in STD_LOGIC;
           address : in STD_LOGIC_VECTOR(7 downto 0);
           data_in : in STD_LOGIC_VECTOR(31 downto 0);
           data_out : out STD_LOGIC_VECTOR(31 downto 0));
end SRAM_with_PowerGating;

architecture Behavioral of SRAM_with_PowerGating is
    type ram_type is array (0 to 255) of STD_LOGIC_VECTOR(31 downto 0);
    signal RAM : ram_type := (others => (others => '0'));
    signal gated_clk : STD_LOGIC;
    signal enable_latch : STD_LOGIC := '0';
    signal power_enable : STD_LOGIC;
begin
    -- クロックゲーティングロジック
    process(clk, reset)
    begin
        if reset = '1' then
            enable_latch <= '0';
        elsif falling_edge(clk) then
            enable_latch <= enable and not power_down;
        end if;
    end process;

    gated_clk <= clk and enable_latch;
    power_enable <= not power_down;

    -- SRAMロジック（パワーゲーティング付き）
    process(gated_clk, power_enable)
    begin
        if power_enable = '0' then
            -- パワーダウンモード：全ての動作を停止
            data_out <= (others => 'Z');
        elsif rising_edge(gated_clk) then
            if write_enable = '1' then
                RAM(to_integer(unsigned(address))) <= data_in;
            end if;
            data_out <= RAM(to_integer(unsigned(address)));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Xilinx FPGA用のライブラリ
library UNISIM;
use UNISIM.VComponents.all;

entity FPGA_ClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC_VECTOR(7 downto 0));
end FPGA_ClockGating;

architecture Behavioral of FPGA_ClockGating is
    signal gated_clk : STD_LOGIC;
    signal enable_sync : STD_LOGIC;
    signal data_reg : STD_LOGIC_VECTOR(7 downto 0);
begin
    -- BUFGCE: グローバルクロックバッファ with enable
    BUFGCE_inst : BUFGCE
    port map (
        O => gated_clk,   -- クロック出力
        I => clk,         -- クロック入力
        CE => enable_sync -- クロックイネーブル
    );

    -- イネーブル信号の同期化
    process(clk, reset)
    begin
        if reset = '1' then
            enable_sync <= '0';
        elsif rising_edge(clk) then
            enable_sync <= enable;
        end if;
    end process;

    -- データ処理ロジック
    process(gated_clk, reset)
    begin
        if reset = '1' then
            data_reg <= (others => '0');
        elsif rising_edge(gated_clk) then
            data_reg <= data_in;
        end if;
    end process;

    data_out <= data_reg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity RealTime_ClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           task_active : in STD_LOGIC_VECTOR(3 downto 0);
           data_in : in STD_LOGIC_VECTOR(31 downto 0);
           data_out : out STD_LOGIC_VECTOR(31 downto 0));
end RealTime_ClockGating;

architecture Behavioral of RealTime_ClockGating is
    type clock_array is array (0 to 3) of STD_LOGIC;
    signal gated_clocks : clock_array;
    signal task_active_sync : STD_LOGIC_VECTOR(3 downto 0);
    signal data_reg : STD_LOGIC_VECTOR(31 downto 0);
begin
    -- タスクアクティブ信号の同期化
    process(clk, reset)
    begin
        if reset = '1' then
            task_active_sync <= (others => '0');
        elsif rising_edge(clk) then
            task_active_sync <= task_active;
        end if;
    end process;

    -- 各タスク用のゲーティドクロック生成
    gen_clocks: for i in 0 to 3 generate
        BUFGCE_inst : BUFGCE
        port map (
            O => gated_clocks(i),
            I => clk,
            CE => task_active_sync(i)
        );
    end generate gen_clocks;

    -- マルチタスクデータ処理ロジック
    process(clk, reset)
    begin
        if reset = '1' then
            data_reg <= (others => '0');
        else
            for i in 0 to 3 loop
                if rising_edge(gated_clocks(i)) then
                    data_reg(8*i+7 downto 8*i) <= data_in(8*i+7 downto 8*i);
                end if;
            end loop;
        end if;
    end process;

    data_out <= data_reg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity GlitchFreeClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           gated_clk : out STD_LOGIC);
end GlitchFreeClockGating;

architecture Behavioral of GlitchFreeClockGating is
    signal enable_sync1, enable_sync2 : STD_LOGIC;
begin
    -- イネーブル信号の2段階同期化
    process(clk, reset)
    begin
        if reset = '1' then
            enable_sync1 <= '0';
            enable_sync2 <= '0';
        elsif falling_edge(clk) then
            enable_sync1 <= enable;
            enable_sync2 <= enable_sync1;
        end if;
    end process;

    -- グリッチフリーなクロックゲーティング
    gated_clk <= clk and enable_sync2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity PipelinedClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC_VECTOR(7 downto 0));
end PipelinedClockGating;

architecture Behavioral of PipelinedClockGating is
    signal enable_sync1, enable_sync2 : STD_LOGIC;
    signal gated_clk : STD_LOGIC;
    signal data_reg1, data_reg2 : STD_LOGIC_VECTOR(7 downto 0);
begin
    -- イネーブル信号の同期化とクロックゲーティング
    process(clk, reset)
    begin
        if reset = '1' then
            enable_sync1 <= '0';
            enable_sync2 <= '0';
        elsif falling_edge(clk) then
            enable_sync1 <= enable;
            enable_sync2 <= enable_sync1;
        end if;
    end process;

    gated_clk <= clk and enable_sync2;

    -- パイプライン化されたデータ処理
    process(clk, reset)
    begin
        if reset = '1' then
            data_reg1 <= (others => '0');
            data_reg2 <= (others => '0');
        elsif rising_edge(clk) then
            data_reg1 <= data_in;
            if enable_sync2 = '1' then
                data_reg2 <= data_reg1;
            end if;
        end if;
    end process;

    data_out <= data_reg2;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity XilinxCompatibleClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC_VECTOR(7 downto 0));
end XilinxCompatibleClockGating;

architecture Behavioral of XilinxCompatibleClockGating is
    signal gated_clk : STD_LOGIC;
    signal enable_latch : STD_LOGIC;
    signal data_reg : STD_LOGIC_VECTOR(7 downto 0);

    -- 合成属性の設定
    attribute KEEP : string;
    attribute KEEP of enable_latch : signal is "TRUE";
begin
    -- Xilinx推奨のクロックゲーティングプリミティブ
    BUFGCE_inst : BUFGCE
    port map (
        O => gated_clk,
        I => clk,
        CE => enable_latch
    );

    -- イネーブルラッチ
    process(clk, enable)
    begin
        if clk = '0' then
            enable_latch <= enable;
        end if;
    end process;

    -- データ処理ロジック
    process(gated_clk, reset)
    begin
        if reset = '1' then
            data_reg <= (others => '0');
        elsif rising_edge(gated_clk) then
            data_reg <= data_in;
        end if;
    end process;

    data_out <= data_reg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity MultiClockDomainSystem is
    Port ( clk_fast : in STD_LOGIC;
           clk_slow : in STD_LOGIC;
           reset : in STD_LOGIC;
           enable_fast : in STD_LOGIC;
           enable_slow : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(15 downto 0);
           data_out : out STD_LOGIC_VECTOR(15 downto 0));
end MultiClockDomainSystem;

architecture Behavioral of MultiClockDomainSystem is
    signal gated_clk_fast, gated_clk_slow : STD_LOGIC;
    signal data_fast, data_slow : STD_LOGIC_VECTOR(15 downto 0);
    signal data_sync : STD_LOGIC_VECTOR(15 downto 0);

    component ClockDomainCrossing is
        Port ( clk_in : in STD_LOGIC;
               clk_out : in STD_LOGIC;
               reset : in STD_LOGIC;
               data_in : in STD_LOGIC_VECTOR(15 downto 0);
               data_out : out STD_LOGIC_VECTOR(15 downto 0));
    end component;
begin
    -- クロックゲーティング
    gated_clk_fast <= clk_fast and enable_fast;
    gated_clk_slow <= clk_slow and enable_slow;

    -- 高速ドメイン処理
    process(gated_clk_fast, reset)
    begin
        if reset = '1' then
            data_fast <= (others => '0');
        elsif rising_edge(gated_clk_fast) then
            data_fast <= std_logic_vector(unsigned(data_in) + 1);
        end if;
    end process;

    -- クロックドメイン間のデータ転送
    CDC : ClockDomainCrossing
    port map (
        clk_in => gated_clk_fast,
        clk_out => gated_clk_slow,
        reset => reset,
        data_in => data_fast,
        data_out => data_sync
    );

    -- 低速ドメイン処理
    process(gated_clk_slow, reset)
    begin
        if reset = '1' then
            data_out <= (others => '0');
        elsif rising_edge(gated_clk_slow) then
            data_out <= std_logic_vector(unsigned(data_sync) * 2);
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity AutoClockGating is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC_VECTOR(7 downto 0));
end AutoClockGating;

architecture Behavioral of AutoClockGating is
    signal gated_clk : STD_LOGIC;
    signal data_reg : STD_LOGIC_VECTOR(7 downto 0);
    signal activity_counter : unsigned(3 downto 0) := (others => '0');
    signal auto_enable : STD_LOGIC := '1';
begin
    -- 自動クロックゲーティング制御
    process(clk, reset)
    begin
        if reset = '1' then
            activity_counter <= (others => '0');
            auto_enable <= '1';
        elsif rising_edge(clk) then
            if data_in /= data_reg then
                activity_counter <= (others => '0');
                auto_enable <= '1';
            elsif activity_counter = 15 then
                auto_enable <= '0';
            else
                activity_counter <= activity_counter + 1;
            end if;
        end if;
    end process;

    gated_clk <= clk and auto_enable;

    -- データ処理
    process(gated_clk, reset)
    begin
        if reset = '1' then
            data_reg <= (others => '0');
        elsif rising_edge(gated_clk) then
            data_reg <= data_in;
        end if;
    end process;

    data_out <= data_reg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity LowPowerModeSystem is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           low_power_mode : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(15 downto 0);
           data_out : out STD_LOGIC_VECTOR(15 downto 0));
end LowPowerModeSystem;

architecture Behavioral of LowPowerModeSystem is
    signal gated_clk_normal, gated_clk_low_power : STD_LOGIC;
    signal data_reg : STD_LOGIC_VECTOR(15 downto 0);
    signal clock_divider : unsigned(3 downto 0) := (others => '0');
    signal slow_clock : STD_LOGIC := '0';
begin
    -- クロック分周器（低電力モード用）
    process(clk, reset)
    begin
        if reset = '1' then
            clock_divider <= (others => '0');
            slow_clock <= '0';
        elsif rising_edge(clk) then
            if clock_divider = 15 then
                clock_divider <= (others => '0');
                slow_clock <= not slow_clock;
            else
                clock_divider <= clock_divider + 1;
            end if;
        end if;
    end process;

    -- モード別クロックゲーティング
    gated_clk_normal <= clk and not low_power_mode;
    gated_clk_low_power <= slow_clock and low_power_mode;

    -- データ処理
    process(gated_clk_normal, gated_clk_low_power, reset)
    begin
        if reset = '1' then
            data_reg <= (others => '0');
        elsif rising_edge(gated_clk_normal) then
            data_reg <= std_logic_vector(unsigned(data_in) + 1);
        elsif rising_edge(gated_clk_low_power) then
            data_reg <= std_logic_vector(unsigned(data_in) / 2);
        end if;
    end process;

    data_out <= data_reg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DynamicFrequencyScaling is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           workload : in STD_LOGIC_VECTOR(1 downto 0);
           data_in : in STD_LOGIC_VECTOR(15 downto 0);
           data_out : out STD_LOGIC_VECTOR(15 downto 0));
end DynamicFrequencyScaling;

architecture Behavioral of DynamicFrequencyScaling is
    signal gated_clk : STD_LOGIC;
    signal data_reg : STD_LOGIC_VECTOR(15 downto 0);
    signal clock_divider : unsigned(5 downto 0) := (others => '0');
    signal divided_clock : STD_LOGIC := '0';
    signal selected_clock : STD_LOGIC;
begin
    -- クロック分周器
    process(clk, reset)
    begin
        if reset = '1' then
            clock_divider <= (others => '0');
            divided_clock <= '0';
        elsif rising_edge(clk) then
            clock_divider <= clock_divider + 1;
            case workload is
                when "00" => divided_clock <= clock_divider(5);  -- 1/64 周波数
                when "01" => divided_clock <= clock_divider(3);  -- 1/16 周波数
                when "10" => divided_clock <= clock_divider(1);  -- 1/4 周波数
                when others => divided_clock <= clk;  -- フル周波数
            end case;
        end if;
    end process;

    -- 動的クロック選択
    with workload select
        selected_clock <= divided_clock when "00" | "01" | "10",
                          clk when others;

    -- クロックゲーティング
    gated_clk <= selected_clock and (workload /= "00");

    -- データ処理
    process(gated_clk, reset)
    begin
        if reset = '1' then
            data_reg <= (others => '0');
        elsif rising_edge(gated_clk) then
            case workload is
                when "00" => data_reg <= data_in;  -- アイドル状態
                when "01" => data_reg <= std_logic_vector(unsigned(data_in) + 1);  -- 軽負荷
                when "10" => data_reg <= std_logic_vector(unsigned(data_in) * 2);  -- 中負荷
                when others => data_reg <= std_logic_vector(unsigned(data_in) * unsigned(data_in));  -- 高負荷
            end case;
        end if;
    end process;

    data_out <= data_reg;
end Behavioral;