VHDLでの階層参照を活用する方法と実践12選

port (
    data_in : in std_logic_vector(7 downto 0)
);

entity adder is
    generic (
        WIDTH : integer := 8
    );
    port (
        a, b : in std_logic_vector(WIDTH-1 downto 0);
        sum : out std_logic_vector(WIDTH-1 downto 0)
    );
end entity;

component component_name is
    port (
        -- ポート宣言
    );
end component;

library work;
use work.all;

-- エンティティの直接参照
u1: entity work.my_entity
    port map (
        -- ポートマッピング
    );

u1: my_component
    generic map (
        WIDTH => 16
    )
    port map (
        -- ポートマッピング
    );

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_8bit is
    port (
        a, b : in std_logic_vector(7 downto 0);
        sum : out std_logic_vector(7 downto 0);
        carry_out : out std_logic
    );
end entity adder_8bit;

architecture Behavioral of adder_8bit is
begin
    process(a, b)
        variable temp : std_logic_vector(8 downto 0);
    begin
        temp := ('0' & a) + ('0' & b);
        sum <= temp(7 downto 0);
        carry_out <= temp(8);
    end process;
end architecture Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top_module is
    port (
        input1, input2 : in std_logic_vector(7 downto 0);
        result : out std_logic_vector(7 downto 0);
        overflow : out std_logic
    );
end entity top_module;

architecture Structural of top_module is
    -- コンポーネント宣言
    component adder_8bit is
        port (
            a, b : in std_logic_vector(7 downto 0);
            sum : out std_logic_vector(7 downto 0);
            carry_out : out std_logic
        );
    end component;

begin
    -- コンポーネントのインスタンス化
    adder_inst: adder_8bit
        port map (
            a => input1,
            b => input2,
            sum => result,
            carry_out => overflow
        );

end architecture Structural;

component full_adder is
    port (
        a, b, cin : in std_logic;
        sum, cout : out std_logic
    );
end component;

FA0: full_adder port map (a => a(0), b => b(0), cin => cin, sum => sum(0), cout => c1);
FA1: full_adder port map (a => a(1), b => b(1), cin => c1, sum => sum(1), cout => c2);
FA2: full_adder port map (a => a(2), b => b(2), cin => c2, sum => sum(2), cout => c3);
FA3: full_adder port map (a => a(3), b => b(3), cin => c3, sum => sum(3), cout => cout);

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- 1ビット全加算器の定義
entity full_adder is
    port (
        a, b, cin : in std_logic;
        sum, cout : out std_logic
    );
end full_adder;

architecture Behavioral of full_adder is
begin
    sum <= a xor b xor cin;
    cout <= (a and b) or (cin and (a xor b));
end Behavioral;

-- 4ビット加算器の定義
entity adder_4bit is
    port (
        a, b : in std_logic_vector(3 downto 0);
        cin : in std_logic;
        sum : out std_logic_vector(3 downto 0);
        cout : out std_logic
    );
end adder_4bit;

architecture Structural of adder_4bit is
    component full_adder is
        port (
            a, b, cin : in std_logic;
            sum, cout : out std_logic
        );
    end component;

    signal c1, c2, c3 : std_logic;
begin
    FA0: full_adder port map (a => a(0), b => b(0), cin => cin, sum => sum(0), cout => c1);
    FA1: full_adder port map (a => a(1), b => b(1), cin => c1, sum => sum(1), cout => c2);
    FA2: full_adder port map (a => a(2), b => b(2), cin => c2, sum => sum(2), cout => c3);
    FA3: full_adder port map (a => a(3), b => b(3), cin => c3, sum => sum(3), cout => cout);
end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity adder_4bit_tb is
end adder_4bit_tb;

architecture Behavioral of adder_4bit_tb is
    component adder_4bit is
        port (
            a, b : in std_logic_vector(3 downto 0);
            cin : in std_logic;
            sum : out std_logic_vector(3 downto 0);
            cout : out std_logic
        );
    end component;

    signal a, b, sum : std_logic_vector(3 downto 0);
    signal cin, cout : std_logic;

    -- 階層参照のための信号
    signal c1, c2, c3 : std_logic;
begin
    -- DUT（Design Under Test）のインスタンス化
    DUT: adder_4bit port map (a => a, b => b, cin => cin, sum => sum, cout => cout);

    -- 階層参照による内部信号へのアクセス
    c1 <= <<signal DUT.FA0.cout : std_logic>>;
    c2 <= <<signal DUT.FA1.cout : std_logic>>;
    c3 <= <<signal DUT.FA2.cout : std_logic>>;

    stim_proc: process
    begin
        -- テストケース1
        a <= "1010"; b <= "0110"; cin <= '0';
        wait for 10 ns;
        assert (sum = "0000" and cout = '1') report "Test case 1 failed" severity error;

        -- テストケース2
        a <= "1111"; b <= "0001"; cin <= '0';
        wait for 10 ns;
        assert (sum = "0000" and cout = '1') report "Test case 2 failed" severity error;

        -- 内部信号の確認
        report "Internal carry signals: c1=" & std_logic'image(c1) & 
               ", c2=" & std_logic'image(c2) & 
               ", c3=" & std_logic'image(c3);

        wait;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity adder_4bit_tb is
end adder_4bit_tb;

architecture Behavioral of adder_4bit_tb is
    component adder_4bit is
        port (
            a, b : in std_logic_vector(3 downto 0);
            cin : in std_logic;
            sum : out std_logic_vector(3 downto 0);
            cout : out std_logic
        );
    end component;

    signal a, b, sum : std_logic_vector(3 downto 0);
    signal cin, cout : std_logic;

begin
    DUT: adder_4bit port map (a => a, b => b, cin => cin, sum => sum, cout => cout);

    stim_proc: process
        variable expected_sum : unsigned(4 downto 0);
        variable error_count : integer := 0;
    begin
        for i in 0 to 15 loop
            for j in 0 to 15 loop
                for k in 0 to 1 loop
                    a <= std_logic_vector(to_unsigned(i, 4));
                    b <= std_logic_vector(to_unsigned(j, 4));
                    cin <= '0' when k = 0 else '1';
                    wait for 10 ns;

                    expected_sum := unsigned('0' & a) + unsigned('0' & b) + unsigned'("0000" & cin);

                    assert (unsigned('0' & sum) = expected_sum(3 downto 0) and cout = std_logic(expected_sum(4)))
                        report "Error: a=" & integer'image(i) & 
                               ", b=" & integer'image(j) & 
                               ", cin=" & std_logic'image(cin) & 
                               ", sum=" & integer'image(to_integer(unsigned(sum))) & 
                               ", cout=" & std_logic'image(cout) & 
                               ", expected=" & integer'image(to_integer(expected_sum))
                        severity error;

                    if (unsigned('0' & sum) /= expected_sum(3 downto 0) or cout /= std_logic(expected_sum(4))) then
                        error_count := error_count + 1;
                    end if;
                end loop;
            end loop;
        end loop;

        report "Simulation completed. Total errors: " & integer'image(error_count);
        wait;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity adder_4bit_tb is
end adder_4bit_tb;

architecture Behavioral of adder_4bit_tb is
    component adder_4bit is
        port (
            a, b : in std_logic_vector(3 downto 0);
            cin : in std_logic;
            sum : out std_logic_vector(3 downto 0);
            cout : out std_logic
        );
    end component;

    signal a, b, sum : std_logic_vector(3 downto 0);
    signal cin, cout : std_logic;

    -- 階層参照用の信号
    signal c1, c2, c3 : std_logic;
    signal fa0_sum, fa1_sum, fa2_sum, fa3_sum : std_logic;
begin
    DUT: adder_4bit port map (a => a, b => b, cin => cin, sum => sum, cout => cout);

    -- 階層参照による内部信号へのアクセス
    c1 <= <<signal DUT.FA0.cout : std_logic>>;
    c2 <= <<signal DUT.FA1.cout : std_logic>>;
    c3 <= <<signal DUT.FA2.cout : std_logic>>;
    fa0_sum <= <<signal DUT.FA0.sum : std_logic>>;
    fa1_sum <= <<signal DUT.FA1.sum : std_logic>>;
    fa2_sum <= <<signal DUT.FA2.sum : std_logic>>;
    fa3_sum <= <<signal DUT.FA3.sum : std_logic>>;

    stim_proc: process
        variable expected_sum : unsigned(4 downto 0);
        variable fa_input : std_logic_vector(2 downto 0);
        variable fa_expected_sum, fa_expected_cout : std_logic;
    begin
        for i in 0 to 15 loop
            for j in 0 to 15 loop
                a <= std_logic_vector(to_unsigned(i, 4));
                b <= std_logic_vector(to_unsigned(j, 4));
                cin <= '0';
                wait for 10 ns;

                expected_sum := unsigned('0' & a) + unsigned('0' & b) + unsigned'("0000" & cin);

                -- 4ビット加算器の出力チェック
                assert (unsigned('0' & sum) = expected_sum(3 downto 0) and cout = std_logic(expected_sum(4)))
                    report "4-bit adder error: a=" & integer'image(i) & 
                           ", b=" & integer'image(j) & 
                           ", expected=" & integer'image(to_integer(expected_sum)) &
                           ", actual=" & integer'image(to_integer(unsigned(sum))) & cout
                    severity error;

                -- 各全加算器の動作チェック
                for k in 0 to 3 loop
                    fa_input := a(k) & b(k) & (cin when k = 0 else 
                                               c1 when k = 1 else
                                               c2 when k = 2 else
                                               c3);
                    fa_expected_sum := fa_input(0) xor fa_input(1) xor fa_input(2);
                    fa_expected_cout := (fa_input(0) and fa_input(1)) or 
                                        (fa_input(2) and (fa_input(0) xor fa_input(1)));

                    assert (
                        (k = 0 and fa0_sum = fa_expected_sum and c1 = fa_expected_cout) or
                        (k = 1 and fa1_sum = fa_expected_sum and c2 = fa_expected_cout) or
                        (k = 2 and fa2_sum = fa_expected_sum and c3 = fa_expected_cout) or
                        (k = 3 and fa3_sum = fa_expected_sum and cout = fa_expected_cout)
                    ) report "Full adder " & integer'image(k) & " error" severity error;
                end loop;
            end loop;
        end loop;

        report "Simulation completed.";
        wait;
    end process;
end Behavioral;

calculator/
│
├── src/
│   ├── top/
│   │   └── calculator_top.vhd
│   ├── arithmetic/
│   │   ├── adder.vhd
│   │   ├── subtractor.vhd
│   │   └── multiplier.vhd
│   ├── control/
│   │   └── control_unit.vhd
│   └── memory/
│       └── register_file.vhd
│
└── testbench/
    ├── calculator_top_tb.vhd
    ├── adder_tb.vhd
    ├── subtractor_tb.vhd
    └── multiplier_tb.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity calculator_top is
    port (
        clk, rst : in std_logic;
        op_code : in std_logic_vector(1 downto 0);
        operand_a, operand_b : in std_logic_vector(7 downto 0);
        result : out std_logic_vector(15 downto 0)
    );
end calculator_top;

architecture Structural of calculator_top is
    component adder is
        port (
            a, b : in std_logic_vector(7 downto 0);
            sum : out std_logic_vector(8 downto 0)
        );
    end component;

    component subtractor is
        port (
            a, b : in std_logic_vector(7 downto 0);
            diff : out std_logic_vector(8 downto 0)
        );
    end component;

    component multiplier is
        port (
            a, b : in std_logic_vector(7 downto 0);
            product : out std_logic_vector(15 downto 0)
        );
    end component;

    component control_unit is
        port (
            clk, rst : in std_logic;
            op_code : in std_logic_vector(1 downto 0);
            result_select : out std_logic_vector(1 downto 0)
        );
    end component;

    signal add_result : std_logic_vector(8 downto 0);
    signal sub_result : std_logic_vector(8 downto 0);
    signal mul_result : std_logic_vector(15 downto 0);
    signal result_select : std_logic_vector(1 downto 0);

begin
    add_inst: adder port map (a => operand_a, b => operand_b, sum => add_result);
    sub_inst: subtractor port map (a => operand_a, b => operand_b, diff => sub_result);
    mul_inst: multiplier port map (a => operand_a, b => operand_b, product => mul_result);
    ctrl_inst: control_unit port map (clk => clk, rst => rst, op_code => op_code, result_select => result_select);

    result <= mul_result when result_select = "11" else
              std_logic_vector(resize(unsigned(add_result), 16)) when result_select = "01" else
              std_logic_vector(resize(unsigned(sub_result), 16)) when result_select = "10" else
              (others => '0');

end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity adder is
    generic (
        WIDTH : integer := 8
    );
    port (
        a, b : in std_logic_vector(WIDTH-1 downto 0);
        sum : out std_logic_vector(WIDTH downto 0)
    );
end adder;

architecture Behavioral of adder is
begin
    sum <= std_logic_vector(resize(unsigned('0' & a) + unsigned('0' & b), WIDTH+1));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity control_unit is
    port (
        clk, rst : in std_logic;
        op_code : in std_logic_vector(1 downto 0);
        result_select : out std_logic_vector(1 downto 0)
    );
end control_unit;

architecture Behavioral of control_unit is
    type state_type is (IDLE, EXECUTE);
    signal current_state, next_state : state_type;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            current_state <= IDLE;
        elsif rising_edge(clk) then
            current_state <= next_state;
        end if;
    end process;

    process(current_state, op_code)
    begin
        case current_state is
            when IDLE =>
                next_state <= EXECUTE;
                result_select <= "00";
            when EXECUTE =>
                next_state <= IDLE;
                result_select <= op_code;
        end case;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity calculator_system is
    generic (
        NUM_UNITS : integer := 4
    );
    port (
        clk, rst : in std_logic;
        op_code : in std_logic_vector(1 downto 0);
        operand_a, operand_b : in std_logic_vector(7 downto 0);
        unit_select : in std_logic_vector(1 downto 0);
        result : out std_logic_vector(15 downto 0)
    );
end calculator_system;

architecture Structural of calculator_system is
    component calculator_top is
        port (
            clk, rst : in std_logic;
            op_code : in std_logic_vector(1 downto 0);
            operand_a, operand_b : in std_logic_vector(7 downto 0);
            result : out std_logic_vector(15 downto 0)
        );
    end component;

    type result_array is array (0 to NUM_UNITS-1) of std_logic_vector(15 downto 0);
    signal unit_results : result_array;

begin
    gen_calc_units: for i in 0 to NUM_UNITS-1 generate
        calc_unit: calculator_top 
            port map (
                clk => clk,
                rst => rst,
                op_code => op_code,
                operand_a => operand_a,
                operand_b => operand_b,
                result => unit_results(i)
            );
    end generate;

    result <= unit_results(to_integer(unsigned(unit_select)));

end Structural;

signal unit_0_result : std_logic_vector(15 downto 0);
...
unit_0_result <= <<signal .calculator_system_inst.gen_calc_units(0).calc_unit.result : std_logic_vector(15 downto 0)>>;

-- 修正前
u_component: my_component port map (
    input => top_input,
    output => top_output
);

-- 修正後
u_component: my_component port map (
    input => top_input,
    output => top_output,
    clock => system_clock  -- 欠落していたクロック信号を追加
);

-- トップレベルエンティティ
entity fir_filter_top is
    port (
        clk : in std_logic;
        rst : in std_logic;
        input : in std_logic_vector(7 downto 0);
        output : out std_logic_vector(15 downto 0)
    );
end entity;

architecture rtl of fir_filter_top is
    component fir_stage is
        port (
            clk : in std_logic;
            rst : in std_logic;
            input : in std_logic_vector(7 downto 0);
            coeff : in std_logic_vector(7 downto 0);
            prev_sum : in std_logic_vector(15 downto 0);
            stage_out : out std_logic_vector(15 downto 0)
        );
    end component;

    type coeff_array is array (0 to 3) of std_logic_vector(7 downto 0);
    constant COEFFS : coeff_array := (x"0A", x"1B", x"2C", x"3D");

    type sum_array is array (0 to 4) of std_logic_vector(15 downto 0);
    signal stage_sums : sum_array;
begin
    stage_sums(0) <= (others => '0');

    gen_stages: for i in 0 to 3 generate
        stage_i: fir_stage
            port map (
                clk => clk,
                rst => rst,
                input => input,
                coeff => COEFFS(i),
                prev_sum => stage_sums(i),
                stage_out => stage_sums(i+1)
            );
    end generate;

    output <= stage_sums(4);
end architecture;

-- FIRステージのエンティティ
entity fir_stage is
    port (
        clk : in std_logic;
        rst : in std_logic;
        input : in std_logic_vector(7 downto 0);
        coeff : in std_logic_vector(7 downto 0);
        prev_sum : in std_logic_vector(15 downto 0);
        stage_out : out std_logic_vector(15 downto 0)
    );
end entity;

architecture rtl of fir_stage is
    signal mult_result : std_logic_vector(15 downto 0);
    signal input_reg : std_logic_vector(7 downto 0);
begin
    process(clk, rst)
    begin
        if rst = '1' then
            input_reg <= (others => '0');
            stage_out <= (others => '0');
        elsif rising_edge(clk) then
            input_reg <= input;
            stage_out <= std_logic_vector(unsigned(prev_sum) + unsigned(mult_result));
        end if;
    end process;

    mult_result <= std_logic_vector(unsigned(input_reg) * unsigned(coeff));
end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fir_filter_tb is
end entity;

architecture sim of fir_filter_tb is
    component fir_filter_top is
        port (
            clk : in std_logic;
            rst : in std_logic;
            input : in std_logic_vector(7 downto 0);
            output : out std_logic_vector(15 downto 0)
        );
    end component;

    signal clk : std_logic := '0';
    signal rst : std_logic := '1';
    signal input : std_logic_vector(7 downto 0) := (others => '0');
    signal output : std_logic_vector(15 downto 0);

    -- 階層参照のための信号
    signal stage_1_out, stage_2_out, stage_3_out : std_logic_vector(15 downto 0);
begin
    uut: fir_filter_top port map (clk, rst, input, output);

    -- クロック生成
    clk <= not clk after 5 ns;

    -- 階層参照による内部信号へのアクセス
    stage_1_out <= <<signal .fir_filter_tb.uut.stage_sums(1) : std_logic_vector(15 downto 0)>>;
    stage_2_out <= <<signal .fir_filter_tb.uut.stage_sums(2) : std_logic_vector(15 downto 0)>>;
    stage_3_out <= <<signal .fir_filter_tb.uut.stage_sums(3) : std_logic_vector(15 downto 0)>>;

    stim_proc: process
    begin
        wait for 100 ns;
        rst <= '0';

        -- テスト入力の生成
        for i in 0 to 255 loop
            input <= std_logic_vector(to_unsigned(i, 8));
            wait for 10 ns;

            -- 内部段階の出力を確認
            report "Input: " & integer'image(i) &
                   " Stage1: " & integer'image(to_integer(unsigned(stage_1_out))) &
                   " Stage2: " & integer'image(to_integer(unsigned(stage_2_out))) &
                   " Stage3: " & integer'image(to_integer(unsigned(stage_3_out))) &
                   " Output: " & integer'image(to_integer(unsigned(output)));
        end loop;

        wait;
    end process;
end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity matrix_multiplier is
    generic (
        MATRIX_SIZE : integer := 4
    );
    port (
        clk : in std_logic;
        rst : in std_logic;
        a_in : in std_logic_vector(7 downto 0);
        b_in : in std_logic_vector(7 downto 0);
        result_out : out std_logic_vector(15 downto 0);
        valid_out : out std_logic
    );
end entity;

architecture rtl of matrix_multiplier is
    type matrix_type is array (0 to MATRIX_SIZE-1, 0 to MATRIX_SIZE-1) of std_logic_vector(7 downto 0);
    signal a_matrix, b_matrix : matrix_type;

    component pe_array is
        generic (
            ARRAY_SIZE : integer := 4
        );
        port (
            clk : in std_logic;
            rst : in std_logic;
            a_in : in std_logic_vector(7 downto 0);
            b_in : in std_logic_vector(7 downto 0);
            result_out : out std_logic_vector(15 downto 0);
            valid_out : out std_logic
        );
    end component;

begin
    pe_array_inst: pe_array
        generic map (ARRAY_SIZE => MATRIX_SIZE)
        port map (
            clk => clk,
            rst => rst,
            a_in => a_in,
            b_in => b_in,
            result_out => result_out,
            valid_out => valid_out
        );

    -- 入力マトリックスの管理（簡略化のため省略）
    -- 実際の実装では、a_inとb_inから適切にa_matrixとb_matrixを構築する必要があります

end architecture;

-- 処理要素（PE）アレイ
entity pe_array is
    generic (
        ARRAY_SIZE : integer := 4
    );
    port (
        clk : in std_logic;
        rst : in std_logic;
        a_in : in std_logic_vector(7 downto 0);
        b_in : in std_logic_vector(7 downto 0);
        result_out : out std_logic_vector(15 downto 0);
        valid_out : out std_logic
    );
end entity;

architecture rtl of pe_array is
    component processing_element is
        port (
            clk : in std_logic;
            rst : in std_logic;
            a : in std_logic_vector(7 downto 0);
            b : in std_logic_vector(7 downto 0);
            sum_in : in std_logic_vector(15 downto 0);
            a_out : out std_logic_vector(7 downto 0);
            b_out : out std_logic_vector(7 downto 0);
            sum_out : out std_logic_vector(15 downto 0)
        );
    end component;

    type pe_matrix_type is array (0 to ARRAY_SIZE-1, 0 to ARRAY_SIZE-1) of std_logic_vector(15 downto 0);
    signal pe_sums : pe_matrix_type;

    type a_matrix_type is array (0 to ARRAY_SIZE-1, 0 to ARRAY_SIZE-1) of std_logic_vector(7 downto 0);
    signal a_matrix : a_matrix_type;

    type b_matrix_type is array (0 to ARRAY_SIZE-1, 0 to ARRAY_SIZE-1) of std_logic_vector(7 downto 0);
    signal b_matrix : b_matrix_type;

begin
    gen_rows: for i in 0 to ARRAY_SIZE-1 generate
        gen_cols: for j in 0 to ARRAY_SIZE-1 generate
            pe_inst: processing_element
                port map (
                    clk => clk,
                    rst => rst,
                    a => a_matrix(i, j),
                    b => b_matrix(i, j),
                    sum_in => pe_sums(i, j),
                    a_out => a_matrix(i, j+1),
                    b_out => b_matrix(i+1, j),
                    sum_out => pe_sums(i, j+1)
                );
        end generate;
    end generate;

    -- 結果の出力と有効信号の生成（簡略化のため省略）
    -- 実際の実装では、pe_sumsの最終要素を適切にresult_outに接続し、
    -- 計算完了時にvalid_outを生成する必要があります

end architecture;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity generic_fifo is
    generic (
        DATA_WIDTH : integer := 8;
        FIFO_DEPTH : integer := 16
    );
    port (
        clk : in std_logic;
        rst : in std_logic;
        wr_en : in std_logic;
        rd_en : in std_logic;
        din : in std_logic_vector(DATA_WIDTH-1 downto 0);
        dout : out std_logic_vector(DATA_WIDTH-1 downto 0);
        full : out std_logic;
        empty : out std_logic
    );
end entity;

architecture rtl of generic_fifo is
    type fifo_memory is array (0 to FIFO_DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
    signal memory : fifo_memory;

    signal read_ptr, write_ptr : unsigned(log2ceil(FIFO_DEPTH)-1 downto 0);
    signal next_read_ptr, next_write_ptr : unsigned(log2ceil(FIFO_DEPTH)-1 downto 0);
    signal count : unsigned(log2ceil(FIFO_DEPTH) downto 0);

    -- log2ceil関数の定義
    function log2ceil(arg : positive) return natural is
        variable temp : positive := 1;
        variable log : natural := 0;
    begin
        while temp < arg loop
            temp := temp * 2;
            log := log + 1;
        end loop;
        return log;
    end function;

begin
    process(clk, rst)
    begin
        if rst = '1' then
            read_ptr <= (others => '0');
            write_ptr <= (others => '0');
            count <= (others => '0');
        elsif rising_edge(clk) then
            if wr_en = '1' and rd_en = '0' and count < FIFO_DEPTH then
                memory(to_integer(write_ptr)) <= din;
                write_ptr <= next_write_ptr;
                count <= count + 1;
            elsif rd_en = '1' and wr_en = '0' and count > 0 then
                read_ptr <= next_read_ptr;
                count <= count - 1;
            elsif wr_en = '1' and rd_en = '1' then
                memory(to_integer(write_ptr)) <= din;
                write_ptr <= next_write_ptr;
                read_ptr <= next_read_ptr;
            end if;
        end if;
    end process;

    next_read_ptr <= (read_ptr + 1) mod FIFO_DEPTH;
    next_write_ptr <= (write_ptr + 1) mod FIFO_DEPTH;

    dout <= memory(to_integer(read_ptr));
    full <= '1' when count = FIFO_DEPTH else '0';
    empty <= '1' when count = 0 else '0';

end architecture;