VHDLシフトレジスタの活用！初心者でもわかる10のステップ

entity shift_register is
    Port ( clk : in STD_LOGIC;
           din : in STD_LOGIC;
           dout : out STD_LOGIC_VECTOR(3 downto 0));
end shift_register;

architecture Behavioral of shift_register is
    signal tmp: STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    process(clk)
    begin
        if rising_edge(clk) then
            tmp <= din & tmp(3 downto 1);
        end if;
    end process;

    dout <= tmp;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity right_shift is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           input_data : in STD_LOGIC_VECTOR(7 downto 0);
           output_data : out STD_LOGIC_VECTOR(7 downto 0));
end right_shift;

architecture Behavioral of right_shift is
signal temp_data : STD_LOGIC_VECTOR(7 downto 0);
begin
process(clk, reset)
begin
    if reset = '1' then
        temp_data <= "00000000";
    elsif rising_edge(clk) then
        temp_data <= input_data(6 downto 0) & "0";
    end if;
end process;

output_data <= temp_data;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity left_shift_register is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           shift : in STD_LOGIC;
           data_out : out STD_LOGIC_VECTOR(7 downto 0));
end left_shift_register;

architecture Behavioral of left_shift_register is
    signal reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    process(clk, rst)
    begin
        if rst = '1' then
            reg <= (others => '0');
        elsif rising_edge(clk) then
            if shift = '1' then
                reg <= data_in(6 downto 0) & "0";
            else
                reg <= data_in;
            end if;
        end if;
    end process;

    data_out <= reg;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter_control is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0));
end counter_control;

architecture Behavioral of counter_control is
    signal temp_count : STD_LOGIC_VECTOR(3 downto 0) := "0000";
begin
    process(clk, reset)
    begin
        if reset = '1' then
            temp_count <= "0000"; --初期化
        elsif rising_edge(clk) then
            temp_count <= temp_count + 1; --カウントアップ
        end if;
    end process;

    count <= temp_count; --出力
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity serial_to_parallel is
    Port ( clk : in STD_LOGIC;
           serial_in : in STD_LOGIC;
           parallel_out : out STD_LOGIC_VECTOR(7 downto 0));
end serial_to_parallel;

architecture Behavioral of serial_to_parallel is
    signal temp_data : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            temp_data <= serial_in & temp_data(7 downto 1); --左シフト
        end if;
    end process;

    parallel_out <= temp_data;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity parallel_conversion is
    Port ( clk : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           data_out1 : out STD_LOGIC_VECTOR(3 downto 0);
           data_out2 : out STD_LOGIC_VECTOR(3 downto 0));
end parallel_conversion;

architecture Behavioral of parallel_conversion is
begin
    data_out1 <= data_in(7 downto 4);
    data_out2 <= data_in(3 downto 0);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity RightShift is
    Port ( clk : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           shifted_data : out STD_LOGIC_VECTOR(7 downto 0));
end RightShift;

architecture Behavioral of RightShift is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            shifted_data <= '0' & data_in(7 downto 1); --右にシフト
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dynamic_shift is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           length_ctrl : in STD_LOGIC_VECTOR(2 downto 0); -- 長さの制御信号
           data_out : out STD_LOGIC_VECTOR(7 downto 0));
end dynamic_shift;

architecture Behavioral of dynamic_shift is
    signal internal_reg : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
    signal length : integer := 8; -- デフォルトの長さ
begin
process(clk, rst)
begin
    if rst = '1' then
        internal_reg <= (others => '0');
    elsif rising_edge(clk) then
        length <= to_integer(length_ctrl); -- 長さの制御信号から長さを設定
        internal_reg(length-1 downto 0) <= data_in(length-1 downto 0);
    end if;
end process;

data_out <= internal_reg;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity led_control is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           led : out STD_LOGIC_VECTOR(7 downto 0));
end led_control;

architecture Behavioral of led_control is
    signal reg : STD_LOGIC_VECTOR(7 downto 0) := "10000000"; -- 初期値
begin
process(clk, rst)
begin
    if rst = '1' then
        reg <= "10000000"; -- リセット時の値
    elsif rising_edge(clk) then
        reg <= reg(6 downto 0) & reg(7); -- 右シフト
    end if;
end process;

led <= reg;

end Behavioral;