VHDL定数活用10選！初心者が今すぐ使えるコード集

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample is
end sample;

architecture Behavioral of sample is
    constant NUM : integer := 10;
    constant MESSAGE : string := "Hello, VHDL!";
begin
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample2 is
end sample2;

architecture Behavioral of sample2 is
    constant BIT_VALUE : STD_LOGIC := '1';
    constant BIT_VECTOR : STD_LOGIC_VECTOR(3 downto 0) := "1100";
begin
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sample3 is
end sample3;

architecture Behavioral of sample3 is
    constant A : integer := 5;
    constant B : integer := 7;
    signal RESULT : integer;
begin
    RESULT <= A + B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity signal_process is
    Port ( input_signal : in STD_LOGIC_VECTOR(7 downto 0);
           output_signal : out STD_LOGIC_VECTOR(7 downto 0) );
end signal_process;

architecture Behavior of signal_process is
    constant ADD_VALUE : STD_LOGIC_VECTOR(7 downto 0) := "00000001"; -- 加算する定数値
begin
    process(input_signal)
    begin
        output_signal <= input_signal + ADD_VALUE; -- 定数を加算
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity module_example is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_out : out STD_LOGIC_VECTOR(3 downto 0) );
end module_example;

architecture Behavior of module_example is
    constant DATA_VALUE : STD_LOGIC_VECTOR(3 downto 0) := "1010"; -- モジュールで使用する定数
begin
    process(clk, rst)
    begin
        if rst = '1' then
            data_out <= "0000";
        elsif rising_edge(clk) then
            data_out <= DATA_VALUE; -- 定数の値を出力
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity condition_example is
    Port ( input_data : in STD_LOGIC_VECTOR(7 downto 0);
           result : out STD_LOGIC );
end condition_example;

architecture Behavior of condition_example is
    constant THRESHOLD : STD_LOGIC_VECTOR(7 downto 0) := "10000000"; -- 閾値として使用する定数
begin
    process(input_data)
    begin
        if input_data > THRESHOLD then
            result <= '1';
        else
            result <= '0';
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity loop_example is
    Port ( clk : in STD_LOGIC;
           led : out STD_LOGIC_VECTOR(7 downto 0));
end loop_example;

architecture behavior of loop_example is
    constant LOOP_COUNT : integer := 10; -- 繰り返し回数を定義
begin
    process(clk)
    begin
        if rising_edge(clk) then
            for i in 1 to LOOP_COUNT loop
                led(i) <= '1'; -- LEDを点灯
                wait for 10 ns;
                led(i) <= '0'; -- LEDを消灯
                wait for 10 ns;
            end loop;
        end if;
    end process;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SampleEntity is
end SampleEntity;

architecture Behavioral of SampleEntity is
    constant CONST_VAL : integer := 10;  -- 定数の宣言
    variable var_val : integer := 5;     -- 変数の宣言
begin
    process
    begin
        var_val := var_val + CONST_VAL;  -- 定数と変数の加算
        report "結果の値: " & integer'image(var_val);  -- 結果をレポートする
        wait;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity CustomSampleEntity is
end CustomSampleEntity;

architecture Behavioral of CustomSampleEntity is
    constant FLOAT_CONST : real := 10.5;  -- 浮動小数点の定数
    variable int_var : integer := 5;     -- 整数型の変数
begin
    process
    begin
        int_var := int_var + to_integer(FLOAT_CONST);  -- 浮動小数点を整数に変換して加算
        report "カスタマイズした結果: " & integer'image(int_var);
        wait;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity AverageFunction is
end AverageFunction;

architecture Behavior of AverageFunction is

  function calculateAverage(x: integer; y: integer) return integer is
    -- 定数の定義
    constant TOTAL_NUMBERS: integer := 2; -- 計算に使用する数値の合計
  begin
    return (x + y) / TOTAL_NUMBERS; -- 平均値を返す
  end function calculateAverage;

begin
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ComplexLogic is
end ComplexLogic;

architecture Behavior of ComplexLogic is
  signal a, b, c, total: integer;

  -- 定数の定義
  constant NUM_SIGNALS: integer := 3; -- 使用する信号の数

  function calculateTotal(x: integer; y: integer; z: integer) return integer is
  begin
    return x + y + z;
  end function calculateTotal;

  function calculateAverage(t: integer) return integer is
  begin
    return t / NUM_SIGNALS;
  end function calculateAverage;

begin
  total <= calculateTotal(a, b, c);
  -- 平均値の計算は、totalの値が更新された後に行う
  average <= calculateAverage(total);
end Behavior;

-- 整数型の定数を宣言
constant INT_VALUE: integer := 10;

-- ビット型の定数を宣言
constant BIT_VALUE: bit := '1';

entity CustomModule is
    generic (CONST_VALUE : integer := 10); -- ジェネリックを利用した定数の定義
port (
    -- 省略
);
end CustomModule;

architecture Behavioral of CustomModule is
begin
    -- この中でCONST_VALUEを使用
    -- 省略
end Behavioral;

myInstance: CustomModule
    generic map (CONST_VALUE => 20)
    port map (
        -- 省略
    );