VHDL初心者必見！generic文の使い方を10のステップで徹底解説

entity SampleEntity is
    generic (DATA_WIDTH : integer := 8);
    port (
        data_in  : in std_logic_vector(DATA_WIDTH-1 downto 0);
        data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end entity SampleEntity;

architecture SampleArch of SampleEntity is
begin
    -- この中でDATA_WIDTHを使ったロジックを記述
end architecture SampleArch;

entity simple_module is
    generic (
        WIDTH : integer := 8
    );
    port (
        a : in std_logic_vector(WIDTH-1 downto 0);
        b : out std_logic_vector(WIDTH-1 downto 0)
    );
end simple_module;

architecture behavior of simple_module is
begin
    -- シンプルなビット幅変更の操作
    b <= a;
end behavior;

entity type_module is
    generic (
        COUNT : integer := 4;
        ENABLE : boolean := true
    );
    port (
        clk : in std_logic;
        rst : in std_logic;
        data : out std_logic_vector(COUNT-1 downto 0)
    );
end type_module;

architecture behavior of type_module is
begin
    process(clk, rst)
    begin
        if rst = '1' then
            data <= (others => '0');
        elsif rising_edge(clk) and ENABLE = true then
            data <= data + 1;
        end if;
    end process;
end behavior;

entity adder is
    generic (
        WIDTH : integer := 8
    );
    port (
        a : in std_logic_vector(WIDTH-1 downto 0);
        b : in std_logic_vector(WIDTH-1 downto 0);
        sum : out std_logic_vector(WIDTH-1 downto 0)
    );
end adder;

architecture behavior of adder is
begin
    sum <= a + b;
end behavior;

entity data_processor is
    generic (
        DATA_WIDTH : integer := 16;
        UNIT_COUNT : integer := 4
    );
    port (
        data_in : in std_logic_vector(DATA_WIDTH*UNIT_COUNT-1 downto 0);
        data_out : out std_logic_vector(DATA_WIDTH*UNIT_COUNT-1 downto 0)
    );
end data_processor;

architecture behavior of data_processor is
begin
    -- ここでは複数のデータユニットでの処理を記述します
    -- サンプルとして簡略化していますが、実際のデザインでは各ユニットでの詳細な処理を記述します
    data_out <= data_in;
end behavior;

entity multi_generic_module is
    generic (
        DATA_WIDTH : integer := 8;
        SHIFT_COUNT : integer := 2
    );
    port (
        data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
        data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end multi_generic_module;

architecture behavior of multi_generic_module is
begin
    data_out <= data_in sll SHIFT_COUNT;
end behavior;

entity adaptive_counter is
    generic (
        MAX_COUNT : integer := 255;
        CLOCK_FREQ : integer := 50
    );
    port (
        clk : in std_logic;
        rst : in std_logic;
        count_out : out std_logic_vector(7 downto 0)
    );
end adaptive_counter;

architecture behavior of adaptive_counter is
    signal count : integer := 0;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            count <= 0;
        elsif rising_edge(clk) then
            if count < MAX_COUNT then
                count <= count + 1;
            else
                count <= 0;
            end if;
        end if;
    end process;

    count_out <= std_logic_vector(to_unsigned(count, 8));
end behavior;

entity conditional_module is
    generic (
        USE_ALTERNATIVE : boolean := false
    );
    port (
        a : in std_logic_vector(7 downto 0);
        b : in std_logic_vector(7 downto 0);
        result : out std_logic_vector(7 downto 0)
    );
end conditional_module;

architecture behavior of conditional_module is
begin
    process(a, b)
    begin
        if USE_ALTERNATIVE = true then
            result <= a and b;
        else
            result <= a or b;
        end if;
    end process;
end behavior;

entity dynamic_memory is
    generic (
        MEMORY_SIZE : integer := 1024;
        ADDR_WIDTH : integer := 10
    );
    port (
        addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
        data : inout std_logic_vector(7 downto 0)
    );
end dynamic_memory;

architecture behavior of dynamic_memory is
    type memory_array is array (0 to MEMORY_SIZE-1) of std_logic_vector(7 downto 0);
    signal mem : memory_array := (others => (others => '0'));
begin
    process(addr)
    begin
        data <= mem(to_integer(unsigned(addr)));
    end process;
end behavior;

entity generic_default is
    generic (
        DATA_WIDTH : integer := 8
    );
    port (
        data_in : in std_logic_vector(DATA_WIDTH-1 downto 0)
    );
end generic_default;

entity generic_counter is
    generic (
        MAX_COUNT : integer := 255
    );
    port (
        count_out : out std_logic_vector(7 downto 0)
    );
end generic_counter;

entity moduleA is
    generic (
        PARAM : integer := 10
    );
end moduleA;

entity moduleB is
    generic (
        PARAM : integer := 10
    );
end moduleB;

entity MyModule is
    generic(
        WIDTH_A : integer := 4;
        WIDTH_B : integer := 8
    );
    port(
        A : in std_logic_vector(WIDTH_A-1 downto 0);
        B : in std_logic_vector(WIDTH_B-1 downto 0);
        C : out std_logic_vector(WIDTH_B-1 downto 0)
    );
end MyModule;

architecture Behavioral of MyModule is
begin
    C <= B & A; -- BとAを結合
end Behavioral;

entity MultiplierModule is
    generic(
        MULTIPLIER : integer := 2
    );
    port(
        X : in std_logic_vector(7 downto 0);
        Y : out std_logic_vector(15 downto 0)
    );
end MultiplierModule;

architecture Behavioral of MultiplierModule is
    signal temp : integer;
begin
    process(X)
    begin
        temp <= to_integer(unsigned(X)) * MULTIPLIER; -- Xの値を倍にする
        Y <= std_logic_vector(to_unsigned(temp, Y'length)); -- 結果をYに格納
    end process;
end Behavioral;