VHDLで学ぶ行動型モデリングの基礎と応用14選

-- エンティティ宣言
entity AND_Gate is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Y : out STD_LOGIC);
end AND_Gate;

-- アーキテクチャ記述
architecture Behavioral of AND_Gate is
begin
    Y <= A and B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DataTypes_Example is
end DataTypes_Example;

architecture Behavioral of DataTypes_Example is
    -- ビット型
    signal my_bit : bit := '0';

    -- ビットベクタ型
    signal my_bit_vector : bit_vector(3 downto 0) := "1010";

    -- std_logic型
    signal my_std_logic : std_logic := 'Z';

    -- std_logic_vector型
    signal my_std_logic_vector : std_logic_vector(7 downto 0) := "10101010";

    -- 整数型
    signal my_integer : integer := 42;

    -- 実数型
    signal my_real : real := 3.14;

    -- 列挙型
    type Color is (Red, Green, Blue);
    signal my_color : Color := Red;

begin
    -- アーキテクチャの本体（この例では空）
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity SignalPort_Example is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           input : in STD_LOGIC;
           output : out STD_LOGIC);
end SignalPort_Example;

architecture Behavioral of SignalPort_Example is
    -- 内部信号の定義
    signal internal_state : STD_LOGIC := '0';
begin
    process(clk, reset)
    begin
        if reset = '1' then
            internal_state <= '0';
        elsif rising_edge(clk) then
            internal_state <= input;
        end if;
    end process;

    -- 出力の割り当て
    output <= internal_state;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Process_Example is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0));
end Process_Example;

architecture Behavioral of Process_Example is
    signal counter : unsigned(3 downto 0) := (others => '0');
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clk) then
            if counter = "1111" then
                counter <= (others => '0');
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    count <= std_logic_vector(counter);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Concurrent_Sequential_Example is
    Port ( A, B, C : in STD_LOGIC;
           X, Y, Z : out STD_LOGIC);
end Concurrent_Sequential_Example;

architecture Behavioral of Concurrent_Sequential_Example is
    signal D : STD_LOGIC;
begin
    -- Concurrent文（並行文）
    X <= A and B;
    D <= B or C;

    -- Sequential文（逐次文）を含むプロセス
    process(A, B, C)
    begin
        if A = '1' then
            Y <= B;
        else
            Y <= C;
        end if;

        Z <= not D;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- エンティティ定義
entity FullAdder is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Cin : in  STD_LOGIC;
           Sum : out  STD_LOGIC;
           Cout : out  STD_LOGIC);
end FullAdder;

-- アーキテクチャ定義
architecture Behavioral of FullAdder is
begin
    Sum <= A xor B xor Cin;
    Cout <= (A and B) or (Cin and (A xor B));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TopLevel is
    Port ( A, B, Cin : in STD_LOGIC;
           Sum, Cout : out STD_LOGIC );
end TopLevel;

architecture Structural of TopLevel is
    -- コンポーネント宣言
    component FullAdder
        Port ( A, B, Cin : in STD_LOGIC;
               Sum, Cout : out STD_LOGIC );
    end component;

begin
    -- コンポーネントのインスタンス化は後ほど行います
end Structural;

architecture Structural of TopLevel is
    component FullAdder
        Port ( A, B, Cin : in STD_LOGIC;
               Sum, Cout : out STD_LOGIC );
    end component;

begin
    -- コンポーネントのインスタンス化
    FA1: FullAdder port map (
        A => A,
        B => B,
        Cin => Cin,
        Sum => Sum,
        Cout => Cout
    );
end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity GenericCounter is
    generic (
        WIDTH : integer := 4
    );
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(WIDTH-1 downto 0) );
end GenericCounter;

architecture Behavioral of GenericCounter is
    signal counter : unsigned(WIDTH-1 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clk) then
            counter <= counter + 1;
        end if;
    end process;

    count <= std_logic_vector(counter);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- 4ビット加算器のエンティティ
entity FourBitAdder is
    Port ( A, B : in STD_LOGIC_VECTOR(3 downto 0);
           Cin : in STD_LOGIC;
           Sum : out STD_LOGIC_VECTOR(3 downto 0);
           Cout : out STD_LOGIC );
end FourBitAdder;

architecture Structural of FourBitAdder is
    -- 全加算器コンポーネントの宣言
    component FullAdder
        Port ( A, B, Cin : in STD_LOGIC;
               Sum, Cout : out STD_LOGIC );
    end component;

    -- 中間キャリー信号の宣言
    signal C : STD_LOGIC_VECTOR(3 downto 0);

begin
    -- 4つの全加算器のインスタンス化
    FA0: FullAdder port map (A(0), B(0), Cin, Sum(0), C(0));
    FA1: FullAdder port map (A(1), B(1), C(0), Sum(1), C(1));
    FA2: FullAdder port map (A(2), B(2), C(1), Sum(2), C(2));
    FA3: FullAdder port map (A(3), B(3), C(2), Sum(3), C(3));

    -- 最終キャリーアウトの割り当て
    Cout <= C(3);
end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Counter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0) );
end Counter;

architecture Behavioral of Counter is
    signal counter : unsigned(3 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clk) then
            counter <= counter + 1;
        end if;
    end process;

    count <= std_logic_vector(counter);

    -- アサーション文の例
    assert counter /= "1111" report "カウンタが最大値に達しました" severity note;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity UpDownCounter is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           up_down : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0) );
end UpDownCounter;

architecture Behavioral of UpDownCounter is
    signal counter : unsigned(3 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= (others => '0');
        elsif rising_edge(clk) then
            if up_down = '1' then
                counter <= counter + 1;
            else
                counter <= counter - 1;
            end if;
        end if;
    end process;

    count <= std_logic_vector(counter);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TrafficLight is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           red, yellow, green : out STD_LOGIC );
end TrafficLight;

architecture Behavioral of TrafficLight is
    type state_type is (S_RED, S_GREEN, S_YELLOW);
    signal state, next_state : state_type;
    signal counter : integer range 0 to 50 := 0;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            state <= S_RED;
            counter <= 0;
        elsif rising_edge(clk) then
            state <= next_state;
            if counter = 50 then
                counter <= 0;
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    process(state, counter)
    begin
        case state is
            when S_RED =>
                red <= '1'; yellow <= '0'; green <= '0';
                if counter = 50 then
                    next_state <= S_GREEN;
                else
                    next_state <= S_RED;
                end if;
            when S_GREEN =>
                red <= '0'; yellow <= '0'; green <= '1';
                if counter = 40 then
                    next_state <= S_YELLOW;
                else
                    next_state <= S_GREEN;
                end if;
            when S_YELLOW =>
                red <= '0'; yellow <= '1'; green <= '0';
                if counter = 10 then
                    next_state <= S_RED;
                else
                    next_state <= S_YELLOW;
                end if;
        end case;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity FIFO is
    generic (
        DATA_WIDTH : integer := 8;
        FIFO_DEPTH : integer := 16
    );
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           write_en : in STD_LOGIC;
           read_en : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
           data_out : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
           empty : out STD_LOGIC;
           full : out STD_LOGIC );
end FIFO;

architecture Behavioral of FIFO is
    type fifo_array is array (0 to FIFO_DEPTH-1) of STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
    signal fifo_mem : fifo_array;
    signal read_ptr, write_ptr : integer range 0 to FIFO_DEPTH-1;
    signal count : integer range 0 to FIFO_DEPTH;
begin
    process(clk, reset)
    begin
        if reset = '1' then
            read_ptr <= 0;
            write_ptr <= 0;
            count <= 0;
        elsif rising_edge(clk) then
            if write_en = '1' and count < FIFO_DEPTH then
                fifo_mem(write_ptr) <= data_in;
                write_ptr <= (write_ptr + 1) mod FIFO_DEPTH;
                count <= count + 1;
            end if;
            if read_en = '1' and count > 0 then
                read_ptr <= (read_ptr + 1) mod FIFO_DEPTH;
                count <= count - 1;
            end if;
        end if;
    end process;

    data_out <= fifo_mem(read_ptr);
    empty <= '1' when count = 0 else '0';
    full <= '1' when count = FIFO_DEPTH else '0';
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity PWM_Controller is
    generic (
        CLK_FREQ : integer := 50_000_000;  -- クロック周波数 (50MHz)
        PWM_FREQ : integer := 10_000       -- PWM周波数 (10kHz)
    );
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           duty_cycle : in STD_LOGIC_VECTOR(7 downto 0);  -- 0-255
           pwm_out : out STD_LOGIC );
end PWM_Controller;

architecture Behavioral of PWM_Controller is
    constant COUNTER_MAX : integer := CLK_FREQ / PWM_FREQ - 1;
    signal counter : integer range 0 to COUNTER_MAX;
    signal pwm_value : unsigned(7 downto 0);
begin
    process(clk, reset)
    begin
        if reset = '1' then
            counter <= 0;
            pwm_out <= '0';
        elsif rising_edge(clk) then
            if counter = COUNTER_MAX then
                counter <= 0;
            else
                counter <= counter + 1;
            end if;

            if counter < pwm_value * COUNTER_MAX / 255 then
                pwm_out <= '1';
            else
                pwm_out <= '0';
            end if;
        end if;
    end process;

    pwm_value <= unsigned(duty_cycle);
end Behavioral;