VHDL二次元配列を完全マスター！10のサンプルコードで徹底解説

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_init is
end array_init;

architecture behavior of array_init is
    type matrix is array (0 to 2, 0 to 2) of integer;
    signal my_matrix : matrix := ((1, 2, 3), (4, 5, 6), (7, 8, 9));
begin
    process
    begin
        for i in 0 to 2 loop
            for j in 0 to 2 loop
                report "my_matrix(" & integer'image(i) & "," & integer'image(j) & ") = " & integer'image(my_matrix(i,j));
            end loop;
        end loop;
        wait;
    end process;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_access is
end array_access;

architecture behavior of array_access is
    type matrix is array (0 to 2, 0 to 2) of integer;
    signal my_matrix : matrix := ((1, 2, 3), (4, 5, 6), (7, 8, 9));
begin
    process
    begin
        my_matrix(1,1) <= 99;
        report "Changed value at (1,1) to " & integer'image(my_matrix(1,1));
        wait;
    end process;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity matrix_multiply is
    Port ( A : in  array (0 to 2, 0 to 2) of integer;
           B : in  array (0 to 2, 0 to 2) of integer;
           C : out array (0 to 2, 0 to 2) of integer);
end matrix_multiply;

architecture behavior of matrix_multiply is
begin
    process(A, B)
    variable sum : integer := 0;
    begin
        for i in 0 to 2 loop
            for j in 0 to 2 loop
                sum := 0;
                for k in 0 to 2 loop
                    sum := sum + A(i, k) * B(k, j);
                end loop;
                C(i, j) := sum;
            end loop;
        end loop;
    end process;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adjust_brightness is
    Port ( Image : in  array (0 to 7, 0 to 7) of integer;
           Adjust : in integer;
           Result : out array (0 to 7, 0 to 7) of integer);
end adjust_brightness;

architecture behavior of adjust_brightness is
begin
    process(Image, Adjust)
    variable temp : integer := 0;
    begin
        for i in 0 to 7 loop
            for j in 0 to 7 loop
                temp := Image(i, j) + Adjust;
                Result(i, j) := temp;
            end loop;
        end loop;
    end process;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DynamicDataStorage is
    Port ( clock : in STD_LOGIC;
           reset : in STD_LOGIC;
           sensor_input : in STD_LOGIC_VECTOR(7 downto 0);
           data_out : out STD_LOGIC_VECTOR(7 downto 0);
           x : in INTEGER range 0 to 9;
           y : in INTEGER range 0 to 9);
end DynamicDataStorage;

architecture Behavior of DynamicDataStorage is
    -- 10x10の二次元配列を定義
    type matrix is array (0 to 9, 0 to 9) of STD_LOGIC_VECTOR(7 downto 0);
    signal data_matrix : matrix := (others => (others => (others => '0')));

begin
    process(clock, reset)
    begin
        if reset = '1' then
            -- リセット時は全データを0に初期化
            data_matrix <= (others => (others => (others => '0')));
        elsif rising_edge(clock) then
            -- クロックの立ち上がりでデータを保存
            data_matrix(x, y) <= sensor_input;
        end if;
    end process;

    -- 指定された位置のデータを出力
    data_out <= data_matrix(x, y);
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Filter2D is
    Port ( 
        input_data: in  array (0 to 4, 0 to 4) of std_logic_vector(7 downto 0);
        filter:     in  array (0 to 2, 0 to 2) of std_logic_vector(7 downto 0);
        output_data: out array (0 to 2, 0 to 2) of std_logic_vector(7 downto 0);
    );
end Filter2D;

architecture Behavioral of Filter2D is
begin
process(input_data, filter)
    variable temp : std_logic_vector(7 downto 0);
begin
    for i in 0 to 2 loop
        for j in 0 to 2 loop
            temp := (others => '0');
            for x in 0 to 2 loop
                for y in 0 to 2 loop
                    temp := temp + input_data(i+x, j+y) * filter(x, y);
                end loop;
            end loop;
            output_data(i,j) := temp;
        end loop;
    end loop;
end process;
end Behavioral;

-- 二次元配列の定義
type char_matrix is array(0 to 3, 0 to 3) of char;

-- エンコード関数
function encode(input_str: string) return char_matrix is
    variable result: char_matrix := (others => (others => ' '));
begin
    for i in 0 to 3 loop
        for j in 0 to 3 loop
            -- 文字列から文字を取得して二次元配列にセット
            result(i, j) := input_str((i*4)+j+1);
        end loop;
    end loop;
    return result;
end function encode;

-- デコード関数
function decode(input_matrix: char_matrix) return string is
    variable result: string(1 to 16);
begin
    for i in 0 to 3 loop
        for j in 0 to 3 loop
            -- 二次元配列から文字を取得して文字列にセット
            result((i*4)+j+1) := input_matrix(i, j);
        end loop;
    end loop;
    return result;
end function decode;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity matrix_sort is
    Port ( clk : in STD_LOGIC;
           start : in STD_LOGIC;
           sorted : out STD_LOGIC_VECTOR(7 downto 0));
end matrix_sort;

architecture Behavioral of matrix_sort is
    type matrix_type is array (3 downto 0, 3 downto 0) of integer;
    signal matrix_data : matrix_type := ((5, 3, 8, 6), 
                                         (1, 7, 4, 2), 
                                         (9, 0, 11, 10), 
                                         (15, 13, 14, 12));
    signal i, j : integer := 0;
    signal temp : integer;
begin
    process(clk, start)
    begin
        if rising_edge(clk) then
            if start = '1' then
                for i in 0 to 3 loop
                    for j in 0 to 2 loop
                        if matrix_data(i, j) > matrix_data(i, j+1) then
                            -- 値を交換
                            temp := matrix_data(i, j);
                            matrix_data(i, j) := matrix_data(i, j+1);
                            matrix_data(i, j+1) := temp;
                        end if;
                    end loop;
                end loop;
            end if;
        end if;
    end process;

    sorted <= matrix_data(0, 0) & matrix_data(0, 1) & matrix_data(0, 2) & matrix_data(0, 3);

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity conversion_table is
    Port ( input : in integer range 0 to 9;
           output : out string(1 to 5));
end conversion_table;

architecture Behavior of conversion_table is
    type table_type is array (0 to 9) of string(1 to 5);
    signal my_table : table_type := (
        "zero", "one", "two", "three", "four", "five", "six", "seven", "eight", "nine");
begin
    process(input)
    begin
        output <= my_table(input);  -- 入力値に基づいて変換テーブルから文字列を取得
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity game_grid is
port (
    x : in integer range 0 to 4; -- x座標
    y : in integer range 0 to 4; -- y座標
    data_in : in std_logic_vector(7 downto 0); -- 入力データ
    data_out : out std_logic_vector(7 downto 0); -- 出力データ
    write_enable : in std_logic; -- 書き込み許可信号
    read_enable : in std_logic -- 読み込み許可信号
);
end game_grid;

architecture behavior of game_grid is
    type grid_array is array (0 to 4, 0 to 4) of std_logic_vector(7 downto 0);
    signal grid_data : grid_array := (others => (others => "00000000"));
begin
    process(write_enable, read_enable)
    begin
        if write_enable = '1' then
            grid_data(x, y) <= data_in;
        elsif read_enable = '1' then
            data_out <= grid_data(x, y);
        end if;
    end process;
end behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity array_size_problem is
end array_size_problem;

architecture Behavioral of array_size_problem is
    type matrix_2x2 is array (0 to 1, 0 to 1) of integer;
    type matrix_3x3 is array (0 to 2, 0 to 2) of integer;
    signal matrix_a: matrix_2x2 := ((1, 2), (3, 4));
    signal matrix_b: matrix_3x3 := ((1, 2, 3), (4, 5, 6), (7, 8, 9));
begin
    -- matrix_a := matrix_b; -- この行はエラーが発生する
end Behavioral;

matrix_a(0,0) := matrix_b(0,0);
matrix_a(0,1) := matrix_b(0,1);
matrix_a(1,0) := matrix_b(1,0);
matrix_a(1,1) := matrix_b(1,1);

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity out_of_range_problem is
end out_of_range_problem;

architecture Behavioral of out_of_range_problem is
    type matrix_2x2 is array (0 to 1, 0 to 1) of integer;
    signal matrix_a: matrix_2x2 := ((1, 2), (3, 4));
begin
    -- matrix_a(2,2) := 5; -- この行はエラーが発生する
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dynamicArray is
end dynamicArray;

architecture Behavior of dynamicArray is
    type matrix is array (0 to 3, 0 to 3) of integer; -- 4x4の初期サイズ
    signal myMatrix : matrix := (others => (others => 0)); -- 初期化
begin
    -- 動的にサイズを変更する処理
    -- この部分は擬似コードで、実際のVHDLには動的なサイズ変更はサポートされていません。
    -- 必要に応じて、新しい配列を定義し、既存のデータをコピーする等の方法を検討する必要があります。
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity extractRow is
end extractRow;

architecture Behavior of extractRow is
    type matrix is array (0 to 3, 0 to 3) of integer; -- 4x4の二次元配列
    type vector is array (0 to 3) of integer; -- 4要素の一次元配列
    signal myMatrix : matrix := (others => (others => 0)); -- 二次元配列の初期化
    signal myVector : vector := (others => 0); -- 一次元配列の初期化
begin
    -- 2行目を抽出
    process
    begin
        for j in 0 to 3 loop
            myVector(j) <= myMatrix(1, j);
        end loop;
    end process;
end Behavior;