5ステップでマスター！VHDLでの平均計算方法

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity average_calc is
    Port ( a : in  integer;
           b : in  integer;
           c : in  integer;
           d : in  integer;
           avg : out integer);
end average_calc;

architecture Behavioral of average_calc is
begin
    avg <= (a + b + c + d) / 4;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity data_avg is
    Port ( data_input : in  STD_LOGIC_VECTOR (7 downto 0);
           data_count : in  STD_LOGIC_VECTOR (3 downto 0);
           avg_output : out STD_LOGIC_VECTOR (7 downto 0));
end data_avg;

architecture Behavior of data_avg is
begin
    process(data_input, data_count)
    variable sum : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
    variable count : INTEGER;
    begin
        for count in 0 to (to_integer(data_count) - 1) loop
            sum := sum + data_input;
        end loop;
        avg_output <= sum(11 downto 4);
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ConditionAverage is
    Port ( data_in : in  STD_LOGIC_VECTOR(7 downto 0);
           avg_out : out STD_LOGIC_VECTOR(7 downto 0);
           clk     : in  STD_LOGIC;
           reset   : in  STD_LOGIC);
end ConditionAverage;

architecture Behavioral of ConditionAverage is
    signal sum : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
    signal count : integer := 0;
begin
process(clk, reset)
begin
    -- クロックが上昇エッジのときの処理
    if rising_edge(clk) then
        -- データが10以上の場合のみ処理
        if data_in >= "00001010" then 
            sum <= sum + data_in;  -- データの累積
            count <= count + 1;    -- 対象データのカウント
        end if;
    elsif reset = '1' then
        sum <= "00000000";
        count <= 0;
    end if;
end process;

process(sum, count)
begin
    -- 平均計算
    if count > 0 then
        avg_out <= sum / count;  -- 総和をカウントで割った値
    else
        avg_out <= "00000000";
    end if;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity moving_average is
    Port ( clk : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           average_out : out STD_LOGIC_VECTOR(7 downto 0));
end moving_average;

architecture Behavioral of moving_average is
    signal data1, data2, sum : STD_LOGIC_VECTOR(7 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            data1 <= data_in;  -- 入力データを保存
            data2 <= data1;    -- 1つ前のデータを保存
            sum <= data_in + data1 + data2;  -- 3点のデータを合計
            average_out <= sum(9 downto 2);  -- 合計を3で割る(右に2ビットシフト)
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity weighted_average is
    Port ( clk : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(7 downto 0);
           average_out : out STD_LOGIC_VECTOR(7 downto 0));
end weighted_average;

architecture Behavioral of weighted_average is
    signal data1, data2, sum : STD_LOGIC_VECTOR(7 downto 0);
begin
    process(clk)
    begin
        if rising_edge(clk) then
            data1 <= data_in;
            data2 <= data1;
            sum <= (data_in * "00000001") + (data1 * "00000010") + (data2 * "00000001");  -- 重みを適用して合計
            average_out <= sum(9 downto 2);
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_calculator is
    Port ( data_in : in STD_LOGIC_VECTOR(7 downto 0);
           result_out : out STD_LOGIC_VECTOR(7 downto 0));
end half_calculator;

architecture Behavioral of half_calculator is
begin
    result_out <= data_in / 2;  -- データを2で割る
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sum_calculator is
    Port ( data1, data2, data3, data4 : in STD_LOGIC_VECTOR(7 downto 0);
           sum_out : out STD_LOGIC_VECTOR(15 downto 0));
end sum_calculator;

architecture Behavioral of sum_calculator is
begin
    sum_out <= ("00000000" & data1) + ("00000000" & data2) + ("00000000" & data3) + ("00000000" & data4);  -- 各データを16ビットに拡張してから合計
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity avg_calc is
    Port ( a : in  integer range 0 to 255;
           b : in  UFIXED(7 downto 0);
           avg : out UFIXED(7 downto 0) );
end avg_calc;

architecture Behavioral of avg_calc is
begin
    process(a, b)
    variable temp_avg : real;
    begin
        -- データ型変換
        temp_avg := (real(a) + to_real(b)) / 2.0;
        avg <= to_ufixed(temp_avg, 7 downto 0);
    end process;
end Behavioral;