VHDLにおける実数を使った除算の実装方法11選

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RealNumberExample is
    Port ( clk : in STD_LOGIC;
           result : out real);
end RealNumberExample;

architecture Behavioral of RealNumberExample is
    -- 変数の宣言と初期化
    variable my_real_var : real := 3.14159;

    -- 信号の宣言
    signal my_real_signal : real;

begin
    process(clk)
    begin
        if rising_edge(clk) then
            -- 信号の初期化
            my_real_signal <= 2.71828;

            -- 実数の演算
            result <= my_real_var * my_real_signal;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RealNumberProcessing is
    Port ( clk : in STD_LOGIC;
           input : in real;
           output : out real);
end RealNumberProcessing;

architecture Behavioral of RealNumberProcessing is
    signal intermediate_result : real;
begin
    process(clk)
        variable temp : real;
    begin
        if rising_edge(clk) then
            -- 変数を使用した中間計算
            temp := input * 2.0;
            temp := temp + 1.5;

            -- 信号に結果を代入
            intermediate_result <= temp;

            -- 出力信号に最終結果を代入
            output <= intermediate_result * 0.5;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;

entity SineWaveGenerator is
    Port ( clk : in STD_LOGIC;
           angle : in real;
           sine_value : out real);
end SineWaveGenerator;

architecture Behavioral of SineWaveGenerator is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            sine_value <= sin(angle);
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity BasicRealDivision is
    Port ( clk : in STD_LOGIC;
           dividend : in real;
           divisor : in real;
           quotient : out real);
end BasicRealDivision;

architecture Behavioral of BasicRealDivision is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if divisor /= 0.0 then
                quotient <= dividend / divisor;
            else
                quotient <= 0.0;  -- ゼロ除算の回避
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ProcessBasedDivision is
    Port ( clk : in STD_LOGIC;
           start : in STD_LOGIC;
           dividend : in real;
           divisor : in real;
           quotient : out real;
           done : out STD_LOGIC);
end ProcessBasedDivision;

architecture Behavioral of ProcessBasedDivision is
    type state_type is (IDLE, DIVIDING, DONE);
    signal state : state_type := IDLE;
    signal temp_quotient : real := 0.0;
    signal iteration : integer := 0;
    constant MAX_ITERATIONS : integer := 10;
begin
    process(clk)
    begin
        if rising_edge(clk) then
            case state is
                when IDLE =>
                    if start = '1' and divisor /= 0.0 then
                        state <= DIVIDING;
                        temp_quotient <= 0.0;
                        iteration <= 0;
                    end if;

                when DIVIDING =>
                    if iteration < MAX_ITERATIONS then
                        temp_quotient <= temp_quotient + (dividend / divisor) / real(MAX_ITERATIONS);
                        iteration <= iteration + 1;
                    else
                        state <= DONE;
                    end if;

                when DONE =>
                    quotient <= temp_quotient;
                    done <= '1';
                    state <= IDLE;
            end case;
        end if;
    end process;
end Behavioral;

-- コンポーネントの定義
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity RealDivisionComponent is
    Port ( clk : in STD_LOGIC;
           start : in STD_LOGIC;
           dividend : in real;
           divisor : in real;
           quotient : out real;
           done : out STD_LOGIC);
end RealDivisionComponent;

architecture Behavioral of RealDivisionComponent is
    -- プロセスを用いた除算の実装（前述のコードと同様）
begin
    -- 実装内容
end Behavioral;

-- コンポーネントの使用例
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DivisionSystem is
    Port ( clk : in STD_LOGIC;
           input_a : in real;
           input_b : in real;
           result : out real);
end DivisionSystem;

architecture Structural of DivisionSystem is
    component RealDivisionComponent is
        Port ( clk : in STD_LOGIC;
               start : in STD_LOGIC;
               dividend : in real;
               divisor : in real;
               quotient : out real;
               done : out STD_LOGIC);
    end component;

    signal start_div, done_div : STD_LOGIC;
    signal temp_result : real;
begin
    DividerInstance: RealDivisionComponent
        port map ( clk => clk,
                   start => start_div,
                   dividend => input_a,
                   divisor => input_b,
                   quotient => temp_result,
                   done => done_div );

    process(clk)
    begin
        if rising_edge(clk) then
            start_div <= '1';  -- 常に除算を開始
            if done_div = '1' then
                result <= temp_result;
            end if;
        end if;
    end process;
end Structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity PipelinedRealDivision is
    Port ( clk : in STD_LOGIC;
           dividend : in real;
           divisor : in real;
           quotient : out real;
           valid_out : out STD_LOGIC);
end PipelinedRealDivision;

architecture Behavioral of PipelinedRealDivision is
    type pipeline_stage is record
        dividend : real;
        divisor : real;
        partial_result : real;
        valid : std_logic;
    end record;

    type pipeline_array is array (0 to 3) of pipeline_stage;
    signal pipeline : pipeline_array := (others => (0.0, 1.0, 0.0, '0'));

begin
    process(clk)
        variable temp_result : real;
    begin
        if rising_edge(clk) then
            -- Stage 0: Input
            pipeline(0).dividend <= dividend;
            pipeline(0).divisor <= divisor;
            pipeline(0).valid <= '1';

            -- Stage 1: Initial approximation
            if pipeline(0).valid = '1' then
                pipeline(1).partial_result <= 1.0 / pipeline(0).divisor;
                pipeline(1).dividend <= pipeline(0).dividend;
                pipeline(1).divisor <= pipeline(0).divisor;
                pipeline(1).valid <= '1';
            else
                pipeline(1).valid <= '0';
            end if;

            -- Stage 2: Newton-Raphson iteration
            if pipeline(1).valid = '1' then
                temp_result := pipeline(1).partial_result * (2.0 - pipeline(1).divisor * pipeline(1).partial_result);
                pipeline(2).partial_result <= temp_result;
                pipeline(2).dividend <= pipeline(1).dividend;
                pipeline(2).valid <= '1';
            else
                pipeline(2).valid <= '0';
            end if;

            -- Stage 3: Final multiplication
            if pipeline(2).valid = '1' then
                quotient <= pipeline(2).dividend * pipeline(2).partial_result;
                valid_out <= '1';
            else
                valid_out <= '0';
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity FixedPointDivision is
    Port ( clk : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(15 downto 0);
           divisor : in STD_LOGIC_VECTOR(15 downto 0);
           quotient : out STD_LOGIC_VECTOR(15 downto 0));
end FixedPointDivision;

architecture Behavioral of FixedPointDivision is
    constant FRACTION_BITS : integer := 8;
begin
    process(clk)
        variable dividend_extended : unsigned(31 downto 0);
        variable divisor_unsigned : unsigned(15 downto 0);
        variable result : unsigned(31 downto 0);
    begin
        if rising_edge(clk) then
            -- 被除数を拡張し、小数点を右にシフト
            dividend_extended := unsigned(dividend) & x"00";
            divisor_unsigned := unsigned(divisor);

            -- 除算を実行
            result := dividend_extended / divisor_unsigned;

            -- 結果を16ビットに切り詰め
            quotient <= std_logic_vector(result(15 downto 0));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity LUTBasedDivision is
    Port ( clk : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(7 downto 0);
           divisor : in STD_LOGIC_VECTOR(3 downto 0);
           quotient : out STD_LOGIC_VECTOR(7 downto 0));
end LUTBasedDivision;

architecture Behavioral of LUTBasedDivision is
    type lut_array is array (0 to 15) of unsigned(7 downto 0);
    constant RECIPROCAL_LUT : lut_array := (
        x"FF", x"80", x"55", x"40", x"33", x"2A", x"24", x"1F",
        x"1C", x"19", x"16", x"14", x"13", x"12", x"11", x"10"
    );
begin
    process(clk)
        variable dividend_unsigned : unsigned(7 downto 0);
        variable divisor_unsigned : unsigned(3 downto 0);
        variable reciprocal : unsigned(7 downto 0);
        variable result : unsigned(15 downto 0);
    begin
        if rising_edge(clk) then
            dividend_unsigned := unsigned(dividend);
            divisor_unsigned := unsigned(divisor);

            -- LUTから逆数を取得
            reciprocal := RECIPROCAL_LUT(to_integer(divisor_unsigned));

            -- 乗算で除算を近似
            result := dividend_unsigned * reciprocal;

            -- 上位8ビットを結果として出力
            quotient <= std_logic_vector(result(15 downto 8));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity NewtonRaphsonDivision is
    Port ( clk : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(15 downto 0);
           divisor : in STD_LOGIC_VECTOR(15 downto 0);
           quotient : out STD_LOGIC_VECTOR(15 downto 0));
end NewtonRaphsonDivision;

architecture Behavioral of NewtonRaphsonDivision is
    constant ITERATIONS : integer := 3;
    constant FIXED_ONE : unsigned(15 downto 0) := x"0100"; -- 1.0 in 8.8 fixed-point
begin
    process(clk)
        variable x : unsigned(15 downto 0);
        variable d : unsigned(15 downto 0);
        variable r : unsigned(15 downto 0);
        variable temp : unsigned(31 downto 0);
    begin
        if rising_edge(clk) then
            x := unsigned(dividend);
            d := unsigned(divisor);

            -- 初期推定値
            r := FIXED_ONE - ("00" & d(15 downto 2));

            -- ニュートン・ラフソン法による反復
            for i in 1 to ITERATIONS loop
                temp := r * (x"0200" - (r * d));
                r := temp(23 downto 8);
            end loop;

            -- 最終的な除算結果
            temp := x * r;
            quotient <= std_logic_vector(temp(23 downto 8));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity IEEE754Division is
    Port ( clk : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(31 downto 0);
           divisor : in STD_LOGIC_VECTOR(31 downto 0);
           quotient : out STD_LOGIC_VECTOR(31 downto 0));
end IEEE754Division;

architecture Behavioral of IEEE754Division is
    function extract_float(input : std_logic_vector(31 downto 0)) return record is
        variable result : record (
            sign : std_logic;
            exponent : unsigned(7 downto 0);
            mantissa : unsigned(22 downto 0);
        );
    begin
        result.sign := input(31);
        result.exponent := unsigned(input(30 downto 23));
        result.mantissa := unsigned(input(22 downto 0));
        return result;
    end function;

    function pack_float(sign : std_logic; exponent : unsigned(7 downto 0); mantissa : unsigned(22 downto 0)) return std_logic_vector is
    begin
        return sign & std_logic_vector(exponent) & std_logic_vector(mantissa);
    end function;

begin
    process(clk)
        variable dividend_parts, divisor_parts, result_parts : record (
            sign : std_logic;
            exponent : unsigned(7 downto 0);
            mantissa : unsigned(22 downto 0);
        );
        variable temp_mantissa : unsigned(23 downto 0);
        variable temp_exponent : integer;
    begin
        if rising_edge(clk) then
            dividend_parts := extract_float(dividend);
            divisor_parts := extract_float(divisor);

            -- 符号ビットの計算
            result_parts.sign := dividend_parts.sign xor divisor_parts.sign;

            -- 指数部の計算
            temp_exponent := to_integer(dividend_parts.exponent) - to_integer(divisor_parts.exponent) + 127;

            -- 仮数部の除算（簡略化のため、1回の除算で代用）
            temp_mantissa := ('1' & dividend_parts.mantissa) / ('1' & divisor_parts.mantissa);

            -- 正規化
            if temp_mantissa(23) = '0' then
                temp_mantissa := temp_mantissa sll 1;
                temp_exponent := temp_exponent - 1;
            end if;

            -- 結果の格納
            result_parts.exponent := to_unsigned(temp_exponent, 8);
            result_parts.mantissa := temp_mantissa(22 downto 0);

            quotient <= pack_float(result_parts.sign, result_parts.exponent, result_parts.mantissa);
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity TimingOptimizedDivision is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(15 downto 0);
           divisor : in STD_LOGIC_VECTOR(15 downto 0);
           quotient : out STD_LOGIC_VECTOR(15 downto 0);
           valid : out STD_LOGIC);
end TimingOptimizedDivision;

architecture Behavioral of TimingOptimizedDivision is
    type stage_type is record
        dividend : unsigned(15 downto 0);
        divisor : unsigned(15 downto 0);
        quotient : unsigned(15 downto 0);
        counter : integer range 0 to 16;
    end record;

    signal stage1, stage2, stage3 : stage_type;
    signal valid_pipe : STD_LOGIC_VECTOR(2 downto 0);
begin
    process(clk, reset)
        variable temp : unsigned(31 downto 0);
    begin
        if reset = '1' then
            stage1 <= (dividend => (others => '0'), divisor => (others => '0'), quotient => (others => '0'), counter => 0);
            stage2 <= (dividend => (others => '0'), divisor => (others => '0'), quotient => (others => '0'), counter => 0);
            stage3 <= (dividend => (others => '0'), divisor => (others => '0'), quotient => (others => '0'), counter => 0);
            valid_pipe <= (others => '0');
        elsif rising_edge(clk) then
            -- Stage 1: 初期化とシフト
            stage1.dividend <= unsigned(dividend);
            stage1.divisor <= unsigned(divisor);
            stage1.quotient <= (others => '0');
            stage1.counter <= 16;
            valid_pipe(0) <= '1';

            -- Stage 2: 減算と商のビット決定
            stage2 <= stage1;
            temp := stage1.dividend & x"0000";
            if temp >= (stage1.divisor & x"0000") then
                stage2.dividend <= temp(31 downto 16) - stage1.divisor;
                stage2.quotient <= stage1.quotient(14 downto 0) & '1';
            else
                stage2.dividend <= temp(31 downto 16);
                stage2.quotient <= stage1.quotient(14 downto 0) & '0';
            end if;
            stage2.counter <= stage1.counter - 1;
            valid_pipe(1) <= valid_pipe(0);

            -- Stage 3: 結果の出力
            stage3 <= stage2;
            valid_pipe(2) <= valid_pipe(1);

            if stage3.counter = 0 then
                quotient <= std_logic_vector(stage3.quotient);
                valid <= '1';
            else
                valid <= '0';
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ResourceEfficientMultiplier is
    Port ( clk : in STD_LOGIC;
           a : in STD_LOGIC_VECTOR(17 downto 0);
           b : in STD_LOGIC_VECTOR(17 downto 0);
           p : out STD_LOGIC_VECTOR(35 downto 0));
end ResourceEfficientMultiplier;

architecture Behavioral of ResourceEfficientMultiplier is
    -- DSPブロックをインスタンス化
    component DSP48E1 is
        port (
            CLK : in STD_LOGIC;
            A : in STD_LOGIC_VECTOR(29 downto 0);
            B : in STD_LOGIC_VECTOR(17 downto 0);
            P : out STD_LOGIC_VECTOR(47 downto 0)
        );
    end component;

    signal a_extended : STD_LOGIC_VECTOR(29 downto 0);
    signal p_internal : STD_LOGIC_VECTOR(47 downto 0);
begin
    -- 入力Aを30ビットに拡張
    a_extended <= std_logic_vector(resize(signed(a), 30));

    -- DSPブロックのインスタンス化
    DSP_MULT : DSP48E1
    port map (
        CLK => clk,
        A => a_extended,
        B => b,
        P => p_internal
    );

    -- 結果の切り詰め
    p <= p_internal(35 downto 0);
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity PowerEfficientDivider is
    Port ( clk : in STD_LOGIC;
           enable : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(15 downto 0);
           divisor : in STD_LOGIC_VECTOR(15 downto 0);
           quotient : out STD_LOGIC_VECTOR(15 downto 0);
           valid : out STD_LOGIC);
end PowerEfficientDivider;

architecture Behavioral of PowerEfficientDivider is
    signal gated_clk : STD_LOGIC;
    signal divider_busy : STD_LOGIC := '0';

    component ClockGate is
        Port ( clk : in STD_LOGIC;
               enable : in STD_LOGIC;
               gated_clk : out STD_LOGIC);
    end component;
begin
    -- クロックゲートのインスタンス化
    ClockGateInst: ClockGate
    port map (
        clk => clk,
        enable => enable or divider_busy,
        gated_clk => gated_clk
    );

    process(gated_clk)
        variable temp_dividend : unsigned(31 downto 0);
        variable temp_divisor : unsigned(15 downto 0);
        variable temp_quotient : unsigned(15 downto 0);
        variable count : integer range 0 to 16;
    begin
        if rising_edge(gated_clk) then
            if enable = '1' and divider_busy = '0' then
                -- 除算の開始
                temp_dividend := unsigned(dividend) & x"0000";
                temp_divisor := unsigned(divisor);
                temp_quotient := (others => '0');
                count := 16;
                divider_busy <= '1';
                valid <= '0';
            elsif divider_busy = '1' then
                -- 除算の実行
                if temp_dividend >= (temp_divisor & x"0000") then
                    temp_dividend := temp_dividend - (temp_divisor & x"0000");
                    temp_quotient := temp_quotient(14 downto 0) & '1';
                else
                    temp_quotient := temp_quotient(14 downto 0) & '0';
                end if;
                temp_dividend := temp_dividend(30 downto 0) & '0';
                count := count - 1;

                if count = 0 then
                    -- 除算の完了
                    quotient <= std_logic_vector(temp_quotient);
                    valid <= '1';
                    divider_busy <= '0';
                end if;
            end if;
        end if;
    end process;
end Behavioral;

-- クロックゲートコンポーネントの定義
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ClockGate is
    Port ( clk : in STD_LOGIC;
           enable : in STD_LOGIC;
           gated_clk : out STD_LOGIC);
end ClockGate;

architecture Behavioral of ClockGate is
    signal latch_out : STD_LOGIC;
begin
    process(clk, enable)
    begin
        if clk = '0' then
            latch_out <= enable;
        end if;
    end process;

    gated_clk <= clk and latch_out;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity ZeroDivisionHandler is
    Port ( clk : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(15 downto 0);
           divisor : in STD_LOGIC_VECTOR(15 downto 0);
           quotient : out STD_LOGIC_VECTOR(15 downto 0);
           error : out STD_LOGIC);
end ZeroDivisionHandler;

architecture Behavioral of ZeroDivisionHandler is
begin
    process(clk)
        variable dividend_unsigned : unsigned(15 downto 0);
        variable divisor_unsigned : unsigned(15 downto 0);
        variable result : unsigned(15 downto 0);
    begin
        if rising_edge(clk) then
            dividend_unsigned := unsigned(dividend);
            divisor_unsigned := unsigned(divisor);

            if divisor_unsigned = 0 then
                -- ゼロ除算の場合
                quotient <= (others => '1');  -- 最大値を出力
                error <= '1';
            else
                -- 通常の除算
                result := dividend_unsigned / divisor_unsigned;
                quotient <= std_logic_vector(result);
                error <= '0';
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity OverflowUnderflowHandler is
    Port ( clk : in STD_LOGIC;
           dividend : in STD_LOGIC_VECTOR(15 downto 0);
           divisor : in STD_LOGIC_VECTOR(15 downto 0);
           quotient : out STD_LOGIC_VECTOR(15 downto 0);
           overflow : out STD_LOGIC;
           underflow : out STD_LOGIC);
end OverflowUnderflowHandler;

architecture Behavioral of OverflowUnderflowHandler is
    constant MAX_VALUE : unsigned(15 downto 0) := x"7FFF";  -- 最大正値
    constant MIN_VALUE : unsigned(15 downto 0) := x"8000";  -- 最小負値
begin
    process(clk)
        variable dividend_signed : signed(31 downto 0);
        variable divisor_signed : signed(15 downto 0);
        variable result : signed(31 downto 0);
    begin
        if rising_edge(clk) then
            dividend_signed := signed(resize(unsigned(dividend), 32));
            divisor_signed := signed(divisor);

            if divisor_signed = 0 then
                -- ゼロ除算の場合
                quotient <= (others => '1');
                overflow <= '1';
                underflow <= '0';
            else
                -- 除算を実行
                result := dividend_signed / divisor_signed;

                -- オーバーフロー・アンダーフローのチェック
                if result > signed(MAX_VALUE) then
                    quotient <= std_logic_vector(MAX_VALUE);
                    overflow <= '1';
                    underflow <= '0';
                elsif result < signed(MIN_VALUE) then
                    quotient <= std_logic_vector(MIN_VALUE);
                    overflow <= '0';
                    underflow <= '1';
                else
                    quotient <= std_logic_vector(result(15 downto 0));
                    overflow <= '0';
                    underflow <= '0';
                end if;
            end if;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;

entity RealDivisionTestBench is
end RealDivisionTestBench;

architecture Behavioral of RealDivisionTestBench is
    -- テスト対象のコンポーネント宣言
    component RealDivision is
        Port ( clk : in STD_LOGIC;
               dividend : in STD_LOGIC_VECTOR(15 downto 0);
               divisor : in STD_LOGIC_VECTOR(15 downto 0);
               quotient : out STD_LOGIC_VECTOR(15 downto 0);
               error : out STD_LOGIC);
    end component;

    -- 信号の宣言
    signal clk : STD_LOGIC := '0';
    signal dividend, divisor, quotient : STD_LOGIC_VECTOR(15 downto 0);
    signal error : STD_LOGIC;

    -- クロック周期の定義
    constant clk_period : time := 10 ns;

begin
    -- テスト対象のインスタンス化
    UUT: RealDivision port map (
        clk => clk,
        dividend => dividend,
        divisor => divisor,
        quotient => quotient,
        error => error
    );

    -- クロック生成プロセス
    clk_process: process
    begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
    end process;

    -- テストプロセス
    stim_proc: process
        variable seed1, seed2 : positive;
        variable rand : real;
        variable int_rand : integer;
    begin
        -- 初期化
        dividend <= (others => '0');
        divisor <= (others => '0');
        wait for 100 ns;

        -- テストケース1: 通常の除算
        dividend <= x"0600"; -- 6.0
        divisor <= x"0200";  -- 2.0
        wait for clk_period;
        assert quotient = x"0300" report "Test case 1 failed" severity error;

        -- テストケース2: ゼロ除算
        dividend <= x"0100"; -- 1.0
        divisor <= x"0000";  -- 0.0
        wait for clk_period;
        assert error = '1' report "Zero division not detected" severity error;

        -- テストケース3: オーバーフロー
        dividend <= x"7FFF"; -- 最大正値
        divisor <= x"0001";  -- 1.0
        wait for clk_period;
        assert quotient = x"7FFF" report "Overflow not handled correctly" severity error;

        -- ランダムテスト
        for i in 1 to 1000 loop
            uniform(seed1, seed2, rand);
            int_rand := integer(rand * 65536.0);
            dividend <= std_logic_vector(to_unsigned(int_rand, 16));

            uniform(seed1, seed2, rand);
            int_rand := integer(rand * 65536.0);
            divisor <= std_logic_vector(to_unsigned(int_rand, 16));

            wait for clk_period;
        end loop;

        -- シミュレーション終了
        wait;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity MovingAverageFilter is
    Generic ( DATA_WIDTH : integer := 16;
              WINDOW_SIZE : integer := 8 );
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           data_in : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
           data_out : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0));
end MovingAverageFilter;

architecture Behavioral of MovingAverageFilter is
    type window_array is array (0 to WINDOW_SIZE-1) of unsigned(DATA_WIDTH-1 downto 0);
    signal window : window_array := (others => (others => '0'));
    signal sum : unsigned(DATA_WIDTH+3 downto 0) := (others => '0');
begin
    process(clk, reset)
        variable new_sum : unsigned(DATA_WIDTH+3 downto 0);
    begin
        if reset = '1' then
            window <= (others => (others => '0'));
            sum <= (others => '0');
            data_out <= (others => '0');
        elsif rising_edge(clk) then
            -- 新しいデータを窓に追加し、古いデータを削除
            new_sum := sum - window(WINDOW_SIZE-1) + unsigned(data_in);
            window <= unsigned(data_in) & window(0 to WINDOW_SIZE-2);
            sum <= new_sum;

            -- 平均値を計算（除算をビットシフトで代用）
            data_out <= std_logic_vector(sum(DATA_WIDTH+3 downto 3));
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity PIDController is
    Generic ( DATA_WIDTH : integer := 16 );
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           setpoint : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
           feedback : in STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
           Kp, Ki, Kd : in STD_LOGIC_VECTOR(7 downto 0);
           control_output : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0));
end PIDController;

architecture Behavioral of PIDController is
    signal error, prev_error : signed(DATA_WIDTH-1 downto 0) := (others => '0');
    signal integral : signed(DATA_WIDTH+7 downto 0) := (others => '0');
    signal derivative : signed(DATA_WIDTH-1 downto 0) := (others => '0');
begin
    process(clk, reset)
        variable p_term, i_term, d_term : signed(DATA_WIDTH+7 downto 0);
        variable output : signed(DATA_WIDTH+7 downto 0);
    begin
        if reset = '1' then
            error <= (others => '0');
            prev_error <= (others => '0');
            integral <= (others => '0');
            derivative <= (others => '0');
            control_output <= (others => '0');
        elsif rising_edge(clk) then
            -- エラーの計算
            error <= signed(setpoint) - signed(feedback);

            -- 積分項の更新
            integral <= integral + error;

            -- 微分項の計算
            derivative <= error - prev_error;

            -- PID項の計算
            p_term := error * signed('0' & Kp);
            i_term := integral * signed('0' & Ki);
            d_term := derivative * signed('0' & Kd);

            -- 制御出力の計算
            output := p_term + i_term + d_term;

            -- 出力の飽和処理
            if output > 2**(DATA_WIDTH-1)-1 then
                control_output <= std_logic_vector(to_unsigned(2**(DATA_WIDTH-1)-1, DATA_WIDTH));
            elsif output < -2**(DATA_WIDTH-1) then
                control_output <= std_logic_vector(to_unsigned(-2**(DATA_WIDTH-1), DATA_WIDTH));
            else
                control_output <= std_logic_vector(output(DATA_WIDTH-1 downto 0));
            end if;

            -- 前回のエラーを更新
            prev_error <= error;
        end if;
    end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;

entity FFT is
    Generic ( N : integer := 8 );  -- FFTのポイント数（2のべき乗）
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           start : in STD_LOGIC;
           x_re, x_im : in STD_LOGIC_VECTOR(15 downto 0);
           y_re, y_im : out STD_LOGIC_VECTOR(15 downto 0);
           done : out STD_LOGIC );
end FFT;

architecture Behavioral of FFT is
    type complex is record
        re : signed(15 downto 0);
        im : signed(15 downto 0);
    end record;

    type complex_array is array (0 to N-1) of complex;
    signal data : complex_array;

    -- 回転因子のテーブル（事前計算）
    type twiddle_factor_array is array (0 to N/2-1) of complex;
    function init_twiddle_factors return twiddle_factor_array is
        variable tf : twiddle_factor_array;
        variable angle : real;
    begin
        for k in 0 to N/2-1 loop
            angle := -2.0 * MATH_PI * real(k) / real(N);
            tf(k).re := to_signed(integer(32767.0 * cos(angle)), 16);
            tf(k).im := to_signed(integer(32767.0 * sin(angle)), 16);
        end loop;
        return tf;
    end function;
    constant twiddle_factors : twiddle_factor_array := init_twiddle_factors;

    -- FFTの状態
    type state_type is (IDLE, LOAD, COMPUTE, OUTPUT);
    signal state : state_type := IDLE;

    signal stage, butterfly : integer := 0;
begin
    process(clk, reset)
        variable temp : complex;
    begin
        if reset = '1' then
            state <= IDLE;
            stage <= 0;
            butterfly <= 0;
            done <= '0';
        elsif rising_edge(clk) then
            case state is
                when IDLE =>
                    if start = '1' then
                        state <= LOAD;
                        stage <= 0;
                        butterfly <= 0;
                    end if;

                when LOAD =>
                    if butterfly < N then
                        data(butterfly).re <= signed(x_re);
                        data(butterfly).im <= signed(x_im);
                        butterfly <= butterfly + 1;
                    else
                        state <= COMPUTE;
                        stage <= 0;
                        butterfly <= 0;
                    end if;

                when COMPUTE =>
                    if stage < log2(N) then
                        if butterfly < N/2 then
                            -- バタフライ演算
                            temp.re := data(butterfly).re + data(butterfly + N/(2**(stage+1))).re;
                            temp.im := data(butterfly).im + data(butterfly + N/(2**(stage+1))).im;

                            data(butterfly + N/(2**(stage+1))).re := data(butterfly).re - data(butterfly + N/(2**(stage+1))).re;
                            data(butterfly + N/(2**(stage+1))).im := data(butterfly).im - data(butterfly + N/(2**(stage+1))).im;

                            data(butterfly) := temp;

                            -- 回転因子との乗算
                            temp.re := (data(butterfly + N/(2**(stage+1))).re * twiddle_factors(butterfly * 2**stage).re - 
                                        data(butterfly + N/(2**(stage+1))).im * twiddle_factors(butterfly * 2**stage).im) / 32768;
                            temp.im := (data(butterfly + N/(2**(stage+1))).re * twiddle_factors(butterfly * 2**stage).im + 
                                        data(butterfly + N/(2**(stage+1))).im * twiddle_factors(butterfly * 2**stage).re) / 32768;

                            data(butterfly + N/(2**(stage+1))) := temp;

                            butterfly <= butterfly + 1;
                        else
                            stage <= stage + 1;
                            butterfly <= 0;
                        end if;
                    else
                        state <= OUTPUT;
                        butterfly <= 0;
                    end if;

                when OUTPUT =>
                    y_re <= std_logic_vector(data(butterfly).re);
                    y_im <= std_logic_vector(data(butterfly).im);
                    if butterfly < N-1 then
                        butterfly <= butterfly + 1;
                    else
                        state <= IDLE;
                        done <= '1';
                    end if;
            end case;
        end if;
    end process;
end Behavioral;