VHDLで剰余操作をマスター！10の実践的サンプルコード

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Modulo is
    Port ( A : in  STD_LOGIC_VECTOR(3 downto 0);
           B : in  STD_LOGIC_VECTOR(3 downto 0);
           Res : out  STD_LOGIC_VECTOR(3 downto 0));
end Modulo;

architecture Behavioral of Modulo is
begin
    Res <= A mod B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BigModulo is
    Port ( A : in  STD_LOGIC_VECTOR(15 downto 0);
           B : in  STD_LOGIC_VECTOR(15 downto 0);
           Res : out  STD_LOGIC_VECTOR(15 downto 0));
end BigModulo;

architecture Behavioral of BigModulo is
begin
    Res <= A mod B;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod_loop is
    Port ( clk : in STD_LOGIC;
           rst : in STD_LOGIC;
           data_out : out integer range 0 to 2);
end mod_loop;

architecture Behavioral of mod_loop is
    signal count : integer range 0 to 9 := 0;
    signal mod_result : integer range 0 to 2;
begin
    process(clk, rst)
    begin
        if rst = '1' then
            count <= 0;
        elsif rising_edge(clk) then
            count <= count + 1;
            mod_result <= count mod 3; -- 剰余計算
        end if;
    end process;

    data_out <= mod_result;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ModuloCheck is
    Port ( num : in  STD_LOGIC_VECTOR (7 downto 0);
           LED : out  STD_LOGIC);
end ModuloCheck;

architecture Behavior of ModuloCheck is
begin
    process(num)
    begin
        -- 3で割り切れるかのチェック
        if (num mod 3 = 0) then 
            LED <= '1'; -- 3で割り切れる場合はLEDを点灯
        else
            LED <= '0'; -- それ以外はLEDを消灯
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BlinkingLED is
    Port ( clk : in STD_LOGIC;
           LED : out  STD_LOGIC);
end BlinkingLED;

architecture Behavior of BlinkingLED is
    signal counter : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
begin
    process(clk)
    begin
        if rising_edge(clk) then 
            counter <= counter + 1;
            -- カウンターが5の倍数のときLEDを点滅
            if (counter mod 5 = 0) then
                LED <= not LED;
            end if;
        end if;
    end process;
end Behavior;

-- データ配列と剰余を設定
constant DATA_ARRAY : array(0 to 9) of integer := (10, 15, 20, 25, 30, 35, 40, 45, 50, 55);
constant REMAINDER : integer := 3;
signal result : integer := 0;

begin
  process
  begin
    for i in DATA_ARRAY'range loop
      -- 剰余3のデータを抽出
      if DATA_ARRAY(i) mod REMAINDER = 0 then
        result <= DATA_ARRAY(i);
      end if;
    end loop;
  end process;
end;

constant BIG_DATA : array(0 to 99) of integer := (others => 0); -- サンプルデータ
constant TARGET_REMAINDER : integer := 5;
signal detected_value : integer := -1; -- -1は未検出の意味

begin
  process
  begin
    for i in BIG_DATA'range loop
      if BIG_DATA(i) mod TARGET_REMAINDER = 0 then
        detected_value <= BIG_DATA(i);
        exit;
      end if;
    end loop;
  end process;
end;

constant SEND_DATA : integer := 58;
constant REMAINDER_VALUE : integer := SEND_DATA mod 7;
signal received_data : integer := 58;
signal received_remainder : integer := 2;
signal is_error : boolean := false;

begin
  process
  begin
    -- 受信データの剰余を計算し、受信剰余と比較
    if received_data mod 7 /= received_remainder then
      is_error <= true;
    end if;
  end process;
end;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity PatternDetect is
    Port ( Data_in  : in  STD_LOGIC_VECTOR(7 downto 0);
           Pattern : in  STD_LOGIC_VECTOR(3 downto 0);
           Match   : out STD_LOGIC);
end PatternDetect;

architecture Behavior of PatternDetect is
begin
    process(Data_in, Pattern)
    variable Temp1 : STD_LOGIC_VECTOR(7 downto 0);
    variable Temp2 : STD_LOGIC_VECTOR(3 downto 0);
    begin
        Temp1 := Data_in mod "10000";   -- 16で剰余を計算
        Temp2 := Temp1(3 downto 0);     -- 下位4ビットを取得

        if Temp2 = Pattern then
            Match <= '1';  -- パターンが一致した場合
        else
            Match <= '0';
        end if;
    end process;
end Behavior;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity WaveformGenerator is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           wave_out : out STD_LOGIC_VECTOR(7 downto 0));
end WaveformGenerator;

architecture Behavioral of WaveformGenerator is
    signal counter : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
begin
    process(clk, rst)
    begin
        if rst = '1' then
            counter <= "00000000";
        elsif rising_edge(clk) then
            counter <= counter + 1;
        end if;
    end process;

    wave_out <= counter mod 50;  -- 50を周期とする波形生成
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ModCalc is
    Port ( input_data : in std_logic_vector(7 downto 0);
           constant_data : in std_logic_vector(7 downto 0);
           result : out std_logic_vector(7 downto 0));
end ModCalc;

architecture Behavior of ModCalc is
begin
    process(input_data, constant_data)
    begin
        -- 一括で剰余計算を行う
        result <= input_data mod constant_data;
    end process;
end Behavior;

-- 剰余を求める関数の定義
function calc_modulus(A: integer; B: integer) return integer is
begin
    -- 0での割り算を避けるための条件チェック
    if B = 0 then
        return -1; -- エラーを示す値として-1を返す
    else
        return A mod B;
    end if;
end function;

-- 高速化のための剰余計算のサンプルコード
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fast_mod is
    Port ( A : in  STD_LOGIC_VECTOR(7 downto 0);
           B : in  STD_LOGIC_VECTOR(7 downto 0);
           Q : out STD_LOGIC_VECTOR(7 downto 0);
           R : out STD_LOGIC_VECTOR(7 downto 0));
end fast_mod;

architecture Behavioral of fast_mod is
begin
    process(A, B)
    begin
        Q <= A / B;  -- 商
        R <= A mod B;  -- 剰余
    end process;
end Behavioral;

-- 精度向上のための剰余計算のサンプルコード
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity precise_mod is
    Port ( A : in  STD_LOGIC_VECTOR(15 downto 0);
           B : in  STD_LOGIC_VECTOR(15 downto 0);
           Q : out STD_LOGIC_VECTOR(15 downto 0);
           R : out STD_LOGIC_VECTOR(15 downto 0));
end precise_mod;

architecture Behavioral of precise_mod is
begin
    process(A, B)
    begin
        Q <= A / B;  -- 商
        R <= A mod B;  -- 剰余
    end process;
end Behavioral;